Yifan Zha 97a3d6090f drm/amdgpu: Program GC registers through RLCG interface in gfx_v11/gmc_v11 ...

[Why]
L1 blocks most of GC registers accessing by MMIO.

[How]
Use RLCG interface to program GC registers under SRIOV VF in full access time.

Signed-off-by: Yifan Zha <Yifan.Zha@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

2022-10-18 22:13:24 -04:00

..

drm

drm/amdgpu: Program GC registers through RLCG interface in gfx_v11/gmc_v11

2022-10-18 22:13:24 -04:00

host1x

gpu: host1x: Use the bitmap API to allocate bitmaps

2022-07-08 17:38:34 +02:00

ipu-v3

Merge tag 'imx-drm-next-2022-05-04' of git://git.pengutronix.de/pza/linux into drm-next

2022-05-06 15:07:39 +10:00

trace

…

vga

…

Makefile

gpu: host1x: Add context bus

2022-06-01 11:50:42 +02:00