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This commit introduces set of information that details the different sets of schedulers available in the SE. Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Christian König <christian.koenig@amd.com> Cc: Timur Kristóf <timur.kristof@gmail.com> Signed-off-by: Rodrigo Siqueira <siqueira@igalia.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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2.4 KiB
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55 lines
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.. _amdgpu-gc:
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========================================
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drm/amdgpu - Graphics and Compute (GC)
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========================================
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The relationship between the CPU and GPU can be described as the
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producer-consumer problem, where the CPU fills out a buffer with operations
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(producer) to be executed by the GPU (consumer). The requested operations in
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the buffer are called **Command Packets**, which can be summarized as a
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compressed way of transmitting command information to the graphics controller.
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The component that acts as the front end between the CPU and the GPU is called
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**Command Processor (CP)**. This component is responsible for providing greater
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flexibility to the **Graphics and Compute (GC)** since CP makes it possible to
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program various aspects of the GPU pipeline. CP also coordinates the
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communication between the CPU and GPU via a mechanism named **Ring Buffers**,
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where the CPU appends information to the buffer while the GPU removes
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operations. CP is also responsible for handling **Indirect Buffers (IB)**.
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For reference, internally the CP consists of several sub-blocks (CPC - CP
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compute, CPG - CP graphics, and CPF - CP fetcher). Some of these acronyms
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appear in register names, but this is more of an implementation detail and not
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something that directly impacts driver programming or debugging.
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Graphics (GFX) and Compute Microcontrollers
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-------------------------------------------
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GC is a large block, and as a result, it has multiple firmware associated with
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it. Some of them are:
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CP (Command Processor)
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The name for the hardware block that encompasses the front end of the
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GFX/Compute pipeline. Consists mainly of a bunch of microcontrollers
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(PFP, ME, CE, MEC). The firmware that runs on these microcontrollers
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provides the driver interface to interact with the GFX/Compute engine.
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MEC (MicroEngine Compute)
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This is the microcontroller that controls the compute queues on the
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GFX/compute engine.
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MES (MicroEngine Scheduler)
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This is the engine for managing queues. For more details check
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:ref:`MicroEngine Scheduler (MES) <amdgpu-mes>`.
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RLC (RunList Controller)
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This is another microcontroller in the GFX/Compute engine. It handles
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power management related functionality within the GFX/Compute engine.
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The name is a vestige of old hardware where it was originally added
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and doesn't really have much relation to what the engine does now.
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.. toctree::
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mes.rst
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