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9365bf006f
Add support to request DRAM bandwidth (BW) with Memory Interconnect in Tegra234 SoC. The DRAM BW required for different modes depends on the link speed (Gen-1/2/3/4) and width/lanes (x1/x2/x4/x8). Currently, the DRAM frequency is always set to the maximum available but that results in the highest power consumption. The Memory Interconnect is a software feature which uses Interconnect framework (ICC). It adds the capability for Memory Controller (MC) clients to request bandwidth and therefore scale DRAM frequency dynamically depending on the required link speed so that the DRAM energy consumption can be optimized. Suggested-by: Manikanta Maddireddy <mmaddireddy@nvidia.com> Signed-off-by: Sumit Gupta <sumitg@nvidia.com> Acked-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com> |
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| .. | ||
| Kconfig | ||
| Makefile | ||
| pci-dra7xx.c | ||
| pci-exynos.c | ||
| pci-imx6.c | ||
| pci-keystone.c | ||
| pci-layerscape-ep.c | ||
| pci-layerscape.c | ||
| pci-meson.c | ||
| pcie-al.c | ||
| pcie-armada8k.c | ||
| pcie-artpec6.c | ||
| pcie-bt1.c | ||
| pcie-designware-ep.c | ||
| pcie-designware-host.c | ||
| pcie-designware-plat.c | ||
| pcie-designware.c | ||
| pcie-designware.h | ||
| pcie-dw-rockchip.c | ||
| pcie-fu740.c | ||
| pcie-hisi.c | ||
| pcie-histb.c | ||
| pcie-intel-gw.c | ||
| pcie-keembay.c | ||
| pcie-kirin.c | ||
| pcie-qcom-ep.c | ||
| pcie-qcom.c | ||
| pcie-spear13xx.c | ||
| pcie-tegra194-acpi.c | ||
| pcie-tegra194.c | ||
| pcie-uniphier-ep.c | ||
| pcie-uniphier.c | ||
| pcie-visconti.c | ||