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0420872478
So far, the SPINAND_PAGE_READ_FROM_CACHE_OP macro was taking a first argument, "fast", which was inducing the possibility to support higher bus frequencies than with the normal (slower) read from cache alternative. In practice, without frequency change on the bus, this was likely without effect, besides perhaps allowing another variant of the same command, that could run at the default highest speed. If we want to support this fully, we need to add a frequency parameter to the slowest command. But before we do that, let's drop the "fast" boolean from the macro and duplicate it, this will further help supporting having different frequencies allowed for each variant. The change is also of course propagated to all users. It has the nice effect to have all macros aligned on the same pattern. Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
264 lines
7.9 KiB
C
264 lines
7.9 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Author:
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* Felix Matouschek <felix@matouschek.org>
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*/
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#include <linux/bitfield.h>
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#include <linux/device.h>
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#include <linux/kernel.h>
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#include <linux/mtd/spinand.h>
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#define SPINAND_MFR_XTX 0x0B
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#define XT26G0XA_STATUS_ECC_MASK GENMASK(5, 2)
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#define XT26G0XA_STATUS_ECC_NO_DETECTED (0 << 2)
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#define XT26G0XA_STATUS_ECC_8_CORRECTED (3 << 4)
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#define XT26G0XA_STATUS_ECC_UNCOR_ERROR (2 << 4)
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#define XT26XXXD_STATUS_ECC3_ECC2_MASK GENMASK(7, 6)
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#define XT26XXXD_STATUS_ECC_NO_DETECTED (0)
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#define XT26XXXD_STATUS_ECC_1_7_CORRECTED (1)
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#define XT26XXXD_STATUS_ECC_8_CORRECTED (3)
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#define XT26XXXD_STATUS_ECC_UNCOR_ERROR (2)
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static SPINAND_OP_VARIANTS(read_cache_variants,
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SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 1, NULL, 0),
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SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
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SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0),
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SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
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SPINAND_PAGE_READ_FROM_CACHE_FAST_OP(0, 1, NULL, 0),
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SPINAND_PAGE_READ_FROM_CACHE_OP(0, 1, NULL, 0));
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static SPINAND_OP_VARIANTS(write_cache_variants,
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SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
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SPINAND_PROG_LOAD(true, 0, NULL, 0));
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static SPINAND_OP_VARIANTS(update_cache_variants,
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SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
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SPINAND_PROG_LOAD(false, 0, NULL, 0));
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static int xt26g0xa_ooblayout_ecc(struct mtd_info *mtd, int section,
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struct mtd_oob_region *region)
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{
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if (section)
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return -ERANGE;
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region->offset = 48;
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region->length = 16;
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return 0;
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}
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static int xt26g0xa_ooblayout_free(struct mtd_info *mtd, int section,
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struct mtd_oob_region *region)
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{
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if (section)
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return -ERANGE;
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region->offset = 1;
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region->length = 47;
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return 0;
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}
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static const struct mtd_ooblayout_ops xt26g0xa_ooblayout = {
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.ecc = xt26g0xa_ooblayout_ecc,
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.free = xt26g0xa_ooblayout_free,
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};
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static int xt26g0xa_ecc_get_status(struct spinand_device *spinand,
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u8 status)
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{
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status = status & XT26G0XA_STATUS_ECC_MASK;
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switch (status) {
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case XT26G0XA_STATUS_ECC_NO_DETECTED:
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return 0;
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case XT26G0XA_STATUS_ECC_8_CORRECTED:
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return 8;
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case XT26G0XA_STATUS_ECC_UNCOR_ERROR:
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return -EBADMSG;
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default:
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break;
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}
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/* At this point values greater than (2 << 4) are invalid */
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if (status > XT26G0XA_STATUS_ECC_UNCOR_ERROR)
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return -EINVAL;
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/* (1 << 2) through (7 << 2) are 1-7 corrected errors */
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return status >> 2;
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}
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static int xt26xxxd_ooblayout_ecc(struct mtd_info *mtd, int section,
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struct mtd_oob_region *region)
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{
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if (section)
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return -ERANGE;
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region->offset = mtd->oobsize / 2;
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region->length = mtd->oobsize / 2;
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return 0;
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}
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static int xt26xxxd_ooblayout_free(struct mtd_info *mtd, int section,
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struct mtd_oob_region *region)
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{
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if (section)
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return -ERANGE;
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region->offset = 2;
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region->length = mtd->oobsize / 2 - 2;
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return 0;
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}
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static const struct mtd_ooblayout_ops xt26xxxd_ooblayout = {
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.ecc = xt26xxxd_ooblayout_ecc,
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.free = xt26xxxd_ooblayout_free,
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};
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static int xt26xxxd_ecc_get_status(struct spinand_device *spinand,
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u8 status)
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{
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switch (FIELD_GET(STATUS_ECC_MASK, status)) {
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case XT26XXXD_STATUS_ECC_NO_DETECTED:
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return 0;
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case XT26XXXD_STATUS_ECC_UNCOR_ERROR:
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return -EBADMSG;
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case XT26XXXD_STATUS_ECC_1_7_CORRECTED:
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return 4 + FIELD_GET(XT26XXXD_STATUS_ECC3_ECC2_MASK, status);
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case XT26XXXD_STATUS_ECC_8_CORRECTED:
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return 8;
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default:
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break;
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}
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return -EINVAL;
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}
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static const struct spinand_info xtx_spinand_table[] = {
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SPINAND_INFO("XT26G01A",
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SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xE1),
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NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
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NAND_ECCREQ(8, 512),
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SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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&write_cache_variants,
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&update_cache_variants),
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SPINAND_HAS_QE_BIT,
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SPINAND_ECCINFO(&xt26g0xa_ooblayout,
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xt26g0xa_ecc_get_status)),
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SPINAND_INFO("XT26G02A",
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SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xE2),
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NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 1, 1, 1),
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NAND_ECCREQ(8, 512),
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SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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&write_cache_variants,
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&update_cache_variants),
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SPINAND_HAS_QE_BIT,
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SPINAND_ECCINFO(&xt26g0xa_ooblayout,
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xt26g0xa_ecc_get_status)),
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SPINAND_INFO("XT26G04A",
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SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xE3),
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NAND_MEMORG(1, 2048, 64, 128, 2048, 40, 1, 1, 1),
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NAND_ECCREQ(8, 512),
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SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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&write_cache_variants,
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&update_cache_variants),
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SPINAND_HAS_QE_BIT,
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SPINAND_ECCINFO(&xt26g0xa_ooblayout,
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xt26g0xa_ecc_get_status)),
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SPINAND_INFO("XT26G01D",
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SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x31),
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NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
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NAND_ECCREQ(8, 512),
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SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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&write_cache_variants,
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&update_cache_variants),
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0,
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SPINAND_ECCINFO(&xt26xxxd_ooblayout,
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xt26xxxd_ecc_get_status)),
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SPINAND_INFO("XT26G11D",
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SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x34),
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NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
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NAND_ECCREQ(8, 512),
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SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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&write_cache_variants,
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&update_cache_variants),
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0,
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SPINAND_ECCINFO(&xt26xxxd_ooblayout,
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xt26xxxd_ecc_get_status)),
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SPINAND_INFO("XT26Q01D",
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SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x51),
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NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
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NAND_ECCREQ(8, 512),
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SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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&write_cache_variants,
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&update_cache_variants),
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0,
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SPINAND_ECCINFO(&xt26xxxd_ooblayout,
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xt26xxxd_ecc_get_status)),
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SPINAND_INFO("XT26G02D",
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SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x32),
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NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
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NAND_ECCREQ(8, 512),
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SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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&write_cache_variants,
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&update_cache_variants),
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0,
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SPINAND_ECCINFO(&xt26xxxd_ooblayout,
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xt26xxxd_ecc_get_status)),
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SPINAND_INFO("XT26G12D",
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SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x35),
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NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
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NAND_ECCREQ(8, 512),
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SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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&write_cache_variants,
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&update_cache_variants),
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0,
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SPINAND_ECCINFO(&xt26xxxd_ooblayout,
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xt26xxxd_ecc_get_status)),
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SPINAND_INFO("XT26Q02D",
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SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x52),
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NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
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NAND_ECCREQ(8, 512),
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SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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&write_cache_variants,
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&update_cache_variants),
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0,
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SPINAND_ECCINFO(&xt26xxxd_ooblayout,
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xt26xxxd_ecc_get_status)),
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SPINAND_INFO("XT26G04D",
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SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x33),
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NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1),
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NAND_ECCREQ(8, 512),
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SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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&write_cache_variants,
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&update_cache_variants),
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0,
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SPINAND_ECCINFO(&xt26xxxd_ooblayout,
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xt26xxxd_ecc_get_status)),
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SPINAND_INFO("XT26Q04D",
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SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x53),
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NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1),
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NAND_ECCREQ(8, 512),
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SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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&write_cache_variants,
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&update_cache_variants),
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0,
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SPINAND_ECCINFO(&xt26xxxd_ooblayout,
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xt26xxxd_ecc_get_status)),
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};
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static const struct spinand_manufacturer_ops xtx_spinand_manuf_ops = {
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};
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const struct spinand_manufacturer xtx_spinand_manufacturer = {
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.id = SPINAND_MFR_XTX,
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.name = "XTX",
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.chips = xtx_spinand_table,
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.nchips = ARRAY_SIZE(xtx_spinand_table),
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.ops = &xtx_spinand_manuf_ops,
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};
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