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0420872478
So far, the SPINAND_PAGE_READ_FROM_CACHE_OP macro was taking a first argument, "fast", which was inducing the possibility to support higher bus frequencies than with the normal (slower) read from cache alternative. In practice, without frequency change on the bus, this was likely without effect, besides perhaps allowing another variant of the same command, that could run at the default highest speed. If we want to support this fully, we need to add a frequency parameter to the slowest command. But before we do that, let's drop the "fast" boolean from the macro and duplicate it, this will further help supporting having different frequencies allowed for each variant. The change is also of course propagated to all users. It has the nice effect to have all macros aligned on the same pattern. Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
148 lines
5.4 KiB
C
148 lines
5.4 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Author:
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* Chuanhong Guo <gch981213@gmail.com> - the main driver logic
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* Martin Kurbanov <mmkurbanov@sberdevices.ru> - OOB layout
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*/
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#include <linux/device.h>
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#include <linux/kernel.h>
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#include <linux/mtd/spinand.h>
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/* ESMT uses GigaDevice 0xc8 JECDEC ID on some SPI NANDs */
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#define SPINAND_MFR_ESMT_C8 0xc8
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static SPINAND_OP_VARIANTS(read_cache_variants,
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SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
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SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
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SPINAND_PAGE_READ_FROM_CACHE_FAST_OP(0, 1, NULL, 0),
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SPINAND_PAGE_READ_FROM_CACHE_OP(0, 1, NULL, 0));
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static SPINAND_OP_VARIANTS(write_cache_variants,
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SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
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SPINAND_PROG_LOAD(true, 0, NULL, 0));
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static SPINAND_OP_VARIANTS(update_cache_variants,
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SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
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SPINAND_PROG_LOAD(false, 0, NULL, 0));
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/*
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* OOB spare area map (64 bytes)
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*
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* Bad Block Markers
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* filled by HW and kernel Reserved
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* | +-----------------------+-----------------------+
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* | | | |
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* | | OOB free data Area |non ECC protected |
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* | +-------------|-----+-----------------|-----+-----------------|-----+
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* | | | | | | | |
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* +-|---|----------+--|-----|--------------+--|-----|--------------+--|-----|--------------+
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* | | | section0 | | | section1 | | | section2 | | | section3 |
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* +-v-+-v-+---+----+--v--+--v--+-----+-----+--v--+--v--+-----+-----+--v--+--v--+-----+-----+
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* | | | | | | | | | | | | | | | | |
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* |0:1|2:3|4:7|8:15|16:17|18:19|20:23|24:31|32:33|34:35|36:39|40:47|48:49|50:51|52:55|56:63|
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* | | | | | | | | | | | | | | | | |
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* +---+---+-^-+--^-+-----+-----+--^--+--^--+-----+-----+--^--+--^--+-----+-----+--^--+--^--+
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* | | | | | | | |
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* | +----------------|-----+-----------------|-----+-----------------|-----+
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* | ECC Area|(Main + Spare) - filled|by ESMT NAND HW |
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* | | | |
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* +---------------------+-----------------------+-----------------------+
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* OOB ECC protected Area - not used due to
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* partial programming from some filesystems
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* (like JFFS2 with cleanmarkers)
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*/
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#define ESMT_OOB_SECTION_COUNT 4
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#define ESMT_OOB_SECTION_SIZE(nand) \
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(nanddev_per_page_oobsize(nand) / ESMT_OOB_SECTION_COUNT)
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#define ESMT_OOB_FREE_SIZE(nand) \
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(ESMT_OOB_SECTION_SIZE(nand) / 2)
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#define ESMT_OOB_ECC_SIZE(nand) \
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(ESMT_OOB_SECTION_SIZE(nand) - ESMT_OOB_FREE_SIZE(nand))
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#define ESMT_OOB_BBM_SIZE 2
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static int f50l1g41lb_ooblayout_ecc(struct mtd_info *mtd, int section,
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struct mtd_oob_region *region)
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{
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struct nand_device *nand = mtd_to_nanddev(mtd);
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if (section >= ESMT_OOB_SECTION_COUNT)
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return -ERANGE;
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region->offset = section * ESMT_OOB_SECTION_SIZE(nand) +
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ESMT_OOB_FREE_SIZE(nand);
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region->length = ESMT_OOB_ECC_SIZE(nand);
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return 0;
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}
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static int f50l1g41lb_ooblayout_free(struct mtd_info *mtd, int section,
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struct mtd_oob_region *region)
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{
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struct nand_device *nand = mtd_to_nanddev(mtd);
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if (section >= ESMT_OOB_SECTION_COUNT)
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return -ERANGE;
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/*
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* Reserve space for bad blocks markers (section0) and
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* reserved bytes (sections 1-3)
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*/
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region->offset = section * ESMT_OOB_SECTION_SIZE(nand) + 2;
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/* Use only 2 non-protected ECC bytes per each OOB section */
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region->length = 2;
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return 0;
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}
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static const struct mtd_ooblayout_ops f50l1g41lb_ooblayout = {
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.ecc = f50l1g41lb_ooblayout_ecc,
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.free = f50l1g41lb_ooblayout_free,
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};
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static const struct spinand_info esmt_c8_spinand_table[] = {
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SPINAND_INFO("F50L1G41LB",
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SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x01, 0x7f,
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0x7f, 0x7f),
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NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
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NAND_ECCREQ(1, 512),
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SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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&write_cache_variants,
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&update_cache_variants),
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0,
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SPINAND_ECCINFO(&f50l1g41lb_ooblayout, NULL)),
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SPINAND_INFO("F50D1G41LB",
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SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x11, 0x7f,
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0x7f, 0x7f),
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NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
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NAND_ECCREQ(1, 512),
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SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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&write_cache_variants,
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&update_cache_variants),
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0,
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SPINAND_ECCINFO(&f50l1g41lb_ooblayout, NULL)),
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SPINAND_INFO("F50D2G41KA",
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SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x51, 0x7f,
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0x7f, 0x7f),
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NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
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NAND_ECCREQ(8, 512),
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SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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&write_cache_variants,
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&update_cache_variants),
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0,
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SPINAND_ECCINFO(&f50l1g41lb_ooblayout, NULL)),
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};
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static const struct spinand_manufacturer_ops esmt_spinand_manuf_ops = {
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};
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const struct spinand_manufacturer esmt_c8_spinand_manufacturer = {
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.id = SPINAND_MFR_ESMT_C8,
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.name = "ESMT",
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.chips = esmt_c8_spinand_table,
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.nchips = ARRAY_SIZE(esmt_c8_spinand_table),
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.ops = &esmt_spinand_manuf_ops,
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};
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