Krzysztof Kozlowski 73f69c6be2 drm/msm/dsi/phy: Do not overwite PHY_CMN_CLK_CFG1 when choosing bitclk source ... PHY_CMN_CLK_CFG1 register has four fields being used in the driver: DSI clock divider, source of bitclk and two for enabling the DSI PHY PLL clocks. dsi_7nm_set_usecase() sets only the source of bitclk, so should leave all other bits untouched. Use newly introduced dsi_pll_cmn_clk_cfg1_update() to update respective bits without overwriting the rest. While shuffling the code, define and use PHY_CMN_CLK_CFG1 bitfields to make the code more readable and obvious. Fixes: 1ef7c99d14 ("drm/msm/dsi: add support for 7nm DSI PHY/PLL") Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/637380/ Link: https://lore.kernel.org/r/20250214-drm-msm-phy-pll-cfg-reg-v3-3-0943b850722c@linaro.org Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>		2025-02-15 11:46:42 -08:00
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dsi_phy_7nm.c	drm/msm/dsi/phy: Do not overwite PHY_CMN_CLK_CFG1 when choosing bitclk source	2025-02-15 11:46:42 -08:00
dsi_phy_10nm.c	drm/msm/dsi: Remove dsi_phy_read/write()	2024-06-23 01:15:39 +03:00
dsi_phy_14nm.c	drm/msm/dsi: Add dsi phy support for SM6150	2024-12-15 14:37:20 +02:00
dsi_phy_20nm.c	drm/msm/dsi: Remove dsi_phy_read/write()	2024-06-23 01:15:39 +03:00
dsi_phy_28nm_8960.c	drm/msm/dsi: Remove dsi_phy_read/write()	2024-06-23 01:15:39 +03:00
dsi_phy_28nm.c	drm/msm/dsi: Add phy configuration for MSM8937	2024-06-25 01:09:09 +03:00
dsi_phy.c	drm/msm/dsi: Add dsi phy support for SM6150	2024-12-15 14:37:20 +02:00
dsi_phy.h	drm/msm/dsi: Add dsi phy support for SM6150	2024-12-15 14:37:20 +02:00