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facde55b6f
We are currently seeing unexpected link trainings with several different
eDP panels. These are caused by these panels stating bad link status in
their dpcd registers. This can be observed by doing following test:
1. Boot up without Xe module loaded
2. Load Xe module with PSR disabled:
$ modprobe xe enable_psr=0
3. Read panel link status register
$ dpcd_reg read --offset 0x200e --count=1
0x200e: 00
4. Enable PSR, sleep for 2 seconds and disable PSR again:
$ echo 0x1 > /sys/kernel/debug/dri/0/i915_edp_psr_debug
$ echo "-1" > /sys/kernel/debug/dri/0000:00:02.0/xe_params/enable_psr
$ echo 0x0 > /sys/kernel/debug/dri/0/i915_edp_psr_debug
$ sleep 2
$ cat /sys/kernel/debug/dri/0/i915_edp_psr_status | grep status
$ echo 0x1 > /sys/kernel/debug/dri/0/i915_edp_psr_debug
Source PSR/PanelReplay status: DEEP_SLEEP [0x80310030]
5. Now read panel link status registers again:
$ dpcd_reg read --offset 0x200e --count=1
0x200e: 80
Workaround this by not trusting link status registers after PSR is enabled
until first short pulse interrupt is received.
v2:
- clear link_ok flag on pipe disable
- remove useless comment
- modify intel_dp_needs_link_retrain return statement
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20241029122415.1789528-1-jouni.hogander@intel.com
70 lines
2.7 KiB
C
70 lines
2.7 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2019 Intel Corporation
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*/
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#ifndef __INTEL_PSR_H__
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#define __INTEL_PSR_H__
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#include <linux/types.h>
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enum fb_op_origin;
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struct drm_connector;
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struct drm_connector_state;
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struct intel_atomic_state;
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struct intel_connector;
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struct intel_crtc;
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struct intel_crtc_state;
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struct intel_display;
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struct intel_dp;
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struct intel_encoder;
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struct intel_plane;
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struct intel_plane_state;
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#define CAN_PANEL_REPLAY(intel_dp) ((intel_dp)->psr.sink_panel_replay_support && \
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(intel_dp)->psr.source_panel_replay_support)
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bool intel_encoder_can_psr(struct intel_encoder *encoder);
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bool intel_psr_needs_aux_io_power(struct intel_encoder *encoder,
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const struct intel_crtc_state *crtc_state);
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void intel_psr_init_dpcd(struct intel_dp *intel_dp);
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void intel_psr_enable_sink(struct intel_dp *intel_dp,
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const struct intel_crtc_state *crtc_state);
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void intel_psr_pre_plane_update(struct intel_atomic_state *state,
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struct intel_crtc *crtc);
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void intel_psr_post_plane_update(struct intel_atomic_state *state,
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struct intel_crtc *crtc);
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void intel_psr_disable(struct intel_dp *intel_dp,
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const struct intel_crtc_state *old_crtc_state);
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int intel_psr_debug_set(struct intel_dp *intel_dp, u64 value);
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void intel_psr_invalidate(struct intel_display *display,
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unsigned frontbuffer_bits,
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enum fb_op_origin origin);
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void intel_psr_flush(struct intel_display *display,
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unsigned frontbuffer_bits,
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enum fb_op_origin origin);
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void intel_psr_init(struct intel_dp *intel_dp);
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void intel_psr_compute_config(struct intel_dp *intel_dp,
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struct intel_crtc_state *crtc_state,
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struct drm_connector_state *conn_state);
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void intel_psr_get_config(struct intel_encoder *encoder,
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struct intel_crtc_state *pipe_config);
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void intel_psr_irq_handler(struct intel_dp *intel_dp, u32 psr_iir);
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void intel_psr_short_pulse(struct intel_dp *intel_dp);
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void intel_psr_wait_for_idle_locked(const struct intel_crtc_state *new_crtc_state);
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bool intel_psr_enabled(struct intel_dp *intel_dp);
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int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
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struct intel_crtc *crtc);
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void intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state *crtc_state);
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void intel_psr_pause(struct intel_dp *intel_dp);
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void intel_psr_resume(struct intel_dp *intel_dp);
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bool intel_psr_needs_block_dc_vblank(const struct intel_crtc_state *crtc_state);
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bool intel_psr_link_ok(struct intel_dp *intel_dp);
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void intel_psr_lock(const struct intel_crtc_state *crtc_state);
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void intel_psr_unlock(const struct intel_crtc_state *crtc_state);
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void intel_psr_connector_debugfs_add(struct intel_connector *connector);
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void intel_psr_debugfs_register(struct intel_display *display);
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#endif /* __INTEL_PSR_H__ */
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