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1443dd3c67
smu->workload_mask is IP specific and should not be messed with in the common code. The mask bits vary across SMU versions. Move all handling of smu->workload_mask in to the backends and simplify the code. Store the user's preference in smu->power_profile_mode which will be reflected in sysfs. For internal driver profile switches for KFD or VCN, just update the workload mask so that the user's preference is retained. Remove all of the extra now unused workload related elements in the smu structure. v2: use refcounts for workload profiles v3: rework based on feedback from Lijo v4: fix the refcount on failure, drop backend mask v5: rework custom handling v6: handle failure cleanup with custom profile v7: Update documentation Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: Kenneth Feng <kenneth.feng@amd.com> Cc: Lijo Lazar <lijo.lazar@amd.com> Cc: stable@vger.kernel.org # 6.11.x
156 lines
5.1 KiB
C
156 lines
5.1 KiB
C
/*
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* Copyright 2020 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#ifndef __SMU_CMN_H__
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#define __SMU_CMN_H__
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#include "amdgpu_smu.h"
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#if defined(SWSMU_CODE_LAYER_L2) || defined(SWSMU_CODE_LAYER_L3) || defined(SWSMU_CODE_LAYER_L4)
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#define FDO_PWM_MODE_STATIC 1
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#define FDO_PWM_MODE_STATIC_RPM 5
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#define SMU_IH_INTERRUPT_ID_TO_DRIVER 0xFE
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#define SMU_IH_INTERRUPT_CONTEXT_ID_BACO 0x2
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#define SMU_IH_INTERRUPT_CONTEXT_ID_AC 0x3
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#define SMU_IH_INTERRUPT_CONTEXT_ID_DC 0x4
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#define SMU_IH_INTERRUPT_CONTEXT_ID_AUDIO_D0 0x5
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#define SMU_IH_INTERRUPT_CONTEXT_ID_AUDIO_D3 0x6
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#define SMU_IH_INTERRUPT_CONTEXT_ID_THERMAL_THROTTLING 0x7
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#define SMU_IH_INTERRUPT_CONTEXT_ID_FAN_ABNORMAL 0x8
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#define SMU_IH_INTERRUPT_CONTEXT_ID_FAN_RECOVERY 0x9
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extern const int link_speed[];
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/* Helper to Convert from PCIE Gen 1/2/3/4/5/6 to 0.1 GT/s speed units */
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static inline int pcie_gen_to_speed(uint32_t gen)
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{
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return ((gen == 0) ? link_speed[0] : link_speed[gen - 1]);
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}
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int smu_cmn_send_msg_without_waiting(struct smu_context *smu,
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uint16_t msg_index,
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uint32_t param);
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int smu_cmn_send_smc_msg_with_param(struct smu_context *smu,
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enum smu_message_type msg,
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uint32_t param,
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uint32_t *read_arg);
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int smu_cmn_send_smc_msg(struct smu_context *smu,
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enum smu_message_type msg,
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uint32_t *read_arg);
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int smu_cmn_send_debug_smc_msg(struct smu_context *smu,
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uint32_t msg);
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int smu_cmn_send_debug_smc_msg_with_param(struct smu_context *smu,
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uint32_t msg, uint32_t param);
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int smu_cmn_wait_for_response(struct smu_context *smu);
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int smu_cmn_to_asic_specific_index(struct smu_context *smu,
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enum smu_cmn2asic_mapping_type type,
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uint32_t index);
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int smu_cmn_feature_is_supported(struct smu_context *smu,
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enum smu_feature_mask mask);
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int smu_cmn_feature_is_enabled(struct smu_context *smu,
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enum smu_feature_mask mask);
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bool smu_cmn_clk_dpm_is_enabled(struct smu_context *smu,
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enum smu_clk_type clk_type);
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int smu_cmn_get_enabled_mask(struct smu_context *smu,
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uint64_t *feature_mask);
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uint64_t smu_cmn_get_indep_throttler_status(
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const unsigned long dep_status,
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const uint8_t *throttler_map);
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int smu_cmn_feature_update_enable_state(struct smu_context *smu,
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uint64_t feature_mask,
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bool enabled);
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int smu_cmn_feature_set_enabled(struct smu_context *smu,
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enum smu_feature_mask mask,
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bool enable);
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size_t smu_cmn_get_pp_feature_mask(struct smu_context *smu,
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char *buf);
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int smu_cmn_set_pp_feature_mask(struct smu_context *smu,
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uint64_t new_mask);
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int smu_cmn_disable_all_features_with_exception(struct smu_context *smu,
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enum smu_feature_mask mask);
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int smu_cmn_get_smc_version(struct smu_context *smu,
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uint32_t *if_version,
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uint32_t *smu_version);
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int smu_cmn_update_table(struct smu_context *smu,
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enum smu_table_id table_index,
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int argument,
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void *table_data,
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bool drv2smu);
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int smu_cmn_write_watermarks_table(struct smu_context *smu);
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int smu_cmn_write_pptable(struct smu_context *smu);
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int smu_cmn_get_metrics_table(struct smu_context *smu,
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void *metrics_table,
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bool bypass_cache);
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int smu_cmn_get_combo_pptable(struct smu_context *smu);
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void smu_cmn_init_soft_gpu_metrics(void *table, uint8_t frev, uint8_t crev);
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int smu_cmn_set_mp1_state(struct smu_context *smu,
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enum pp_mp1_state mp1_state);
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/*
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* Helper function to make sysfs_emit_at() happy. Align buf to
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* the current page boundary and record the offset.
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*/
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static inline void smu_cmn_get_sysfs_buf(char **buf, int *offset)
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{
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if (!*buf || !offset)
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return;
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*offset = offset_in_page(*buf);
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*buf -= *offset;
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}
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bool smu_cmn_is_audio_func_enabled(struct amdgpu_device *adev);
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void smu_cmn_generic_soc_policy_desc(struct smu_dpm_policy *policy);
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void smu_cmn_generic_plpd_policy_desc(struct smu_dpm_policy *policy);
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void smu_cmn_get_backend_workload_mask(struct smu_context *smu,
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u32 workload_mask,
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u32 *backend_workload_mask);
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#endif
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#endif
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