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mirror of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git synced 2025-09-04 20:19:47 +08:00
linux/drivers/gpu/drm/amd/display/dc/dccg
Ovidiu Bunea a3e6079bd9 drm/amd/display: Remove PIPE_DTO_SRC_SEL programming from set_dtbclk_dto
There are cases where an OTG is remapped from driving a regular HDMI
display to a DP/eDP display. There are also cases where DTBCLK needs to
be enabled for HPO, but DTBCLK DTO programming may be done while OTG is
still enabled which is dangerous as the PIPE_DTO_SRC_SEL programming may
change the pixel clock generator source for a mapped and running OTG and
cause it to hang.

Remove the PIPE_DTO_SRC_SEL programming from this sequence since it is
already done in program_pixel_clk(). Additionally, make sure that
program_pixel_clk sets DTBCLK DTO as source for special HDMI cases.

Cc: stable@vger.kernel.org # 6.11+
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Ovidiu Bunea <Ovidiu.Bunea@amd.com>
Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-11-20 09:41:22 -05:00
..
dcn20 drm/amd/display: Fix flickering caused by dccg 2024-09-02 11:39:53 -04:00
dcn21
dcn30
dcn31 drm/amd/display: Adjust incorrect indentations and spaces 2024-05-20 16:19:34 -04:00
dcn32 drm/amd/display: Keep VBios pixel rate div setting until next mode set 2024-06-05 11:04:50 -04:00
dcn35 drm/amd/display: Remove PIPE_DTO_SRC_SEL programming from set_dtbclk_dto 2024-11-20 09:41:22 -05:00
dcn201
dcn301
dcn302
dcn303
dcn314 drm/amd/display: Keep VBios pixel rate div setting until next mode set 2024-06-05 11:04:50 -04:00
dcn401 drm/amd/display: Configure DTBCLK_P with OPTC only for dcn401 2024-10-01 17:38:17 -04:00
Makefile drm/amd/display: Refactor DCN401 DCCG into component directory 2024-05-13 15:46:35 -04:00