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98f5a44326
Use the pt_dmaengine_register function to register a AE4DMA DMA engine. Reviewed-by: Raju Rangoju <Raju.Rangoju@amd.com> Reviewed-by: Philipp Stanner <pstanner@redhat.com> Signed-off-by: Basavaraj Natikar <Basavaraj.Natikar@amd.com> Link: https://lore.kernel.org/r/20241025095931.726018-5-Basavaraj.Natikar@amd.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
101 lines
1.9 KiB
C
101 lines
1.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* AMD AE4DMA driver
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*
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* Copyright (c) 2024, Advanced Micro Devices, Inc.
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* All Rights Reserved.
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*
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* Author: Basavaraj Natikar <Basavaraj.Natikar@amd.com>
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*/
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#ifndef __AE4DMA_H__
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#define __AE4DMA_H__
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#include <linux/device.h>
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#include <linux/dmaengine.h>
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#include <linux/dmapool.h>
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#include <linux/list.h>
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#include <linux/mutex.h>
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#include <linux/pci.h>
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#include <linux/spinlock.h>
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#include <linux/wait.h>
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#include "../ptdma/ptdma.h"
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#include "../../virt-dma.h"
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#define MAX_AE4_HW_QUEUES 16
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#define AE4_DESC_COMPLETED 0x03
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#define AE4_MAX_IDX_OFF 0x08
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#define AE4_RD_IDX_OFF 0x0c
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#define AE4_WR_IDX_OFF 0x10
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#define AE4_INTR_STS_OFF 0x14
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#define AE4_Q_BASE_L_OFF 0x18
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#define AE4_Q_BASE_H_OFF 0x1c
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#define AE4_Q_SZ 0x20
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#define AE4_DMA_VERSION 4
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#define CMD_AE4_DESC_DW0_VAL 2
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struct ae4_msix {
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int msix_count;
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struct msix_entry msix_entry[MAX_AE4_HW_QUEUES];
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};
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struct ae4_cmd_queue {
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struct ae4_device *ae4;
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struct pt_cmd_queue cmd_q;
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struct list_head cmd;
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/* protect command operations */
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struct mutex cmd_lock;
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struct delayed_work p_work;
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struct workqueue_struct *pws;
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struct completion cmp;
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wait_queue_head_t q_w;
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atomic64_t intr_cnt;
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atomic64_t done_cnt;
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u64 q_cmd_count;
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u32 dridx;
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u32 tail_wi;
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u32 id;
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};
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union dwou {
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u32 dw0;
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struct dword0 {
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u8 byte0;
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u8 byte1;
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u16 timestamp;
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} dws;
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};
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struct dword1 {
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u8 status;
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u8 err_code;
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u16 desc_id;
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};
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struct ae4dma_desc {
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union dwou dwouv;
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struct dword1 dw1;
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u32 length;
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u32 rsvd;
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u32 src_hi;
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u32 src_lo;
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u32 dst_hi;
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u32 dst_lo;
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};
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struct ae4_device {
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struct pt_device pt;
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struct ae4_msix *ae4_msix;
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struct ae4_cmd_queue ae4cmd_q[MAX_AE4_HW_QUEUES];
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unsigned int ae4_irq[MAX_AE4_HW_QUEUES];
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unsigned int cmd_q_count;
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};
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int ae4_core_init(struct ae4_device *ae4);
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void ae4_destroy_work(struct ae4_device *ae4);
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void ae4_check_status_error(struct ae4_cmd_queue *ae4cmd_q, int idx);
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#endif
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