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8090804045
Add definition for the PLL found on SpacemiT K1 SoC, which takes the external 24MHz oscillator as input and generates clocks in various frequencies for the system. Signed-off-by: Haylen Chu <heylenay@4d2.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Alex Elder <elder@riscstar.com> Reviewed-by: Yixun Lan <dlan@gentoo.org> Link: https://lore.kernel.org/r/20250416135406.16284-3-heylenay@4d2.org Signed-off-by: Yixun Lan <dlan@gentoo.org>
248 lines
5.7 KiB
C
248 lines
5.7 KiB
C
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (C) 2024-2025 Haylen Chu <heylenay@outlook.com>
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*/
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#ifndef _DT_BINDINGS_SPACEMIT_CCU_H_
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#define _DT_BINDINGS_SPACEMIT_CCU_H_
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/* APBS (PLL) clocks */
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#define CLK_PLL1 0
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#define CLK_PLL2 1
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#define CLK_PLL3 2
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#define CLK_PLL1_D2 3
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#define CLK_PLL1_D3 4
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#define CLK_PLL1_D4 5
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#define CLK_PLL1_D5 6
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#define CLK_PLL1_D6 7
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#define CLK_PLL1_D7 8
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#define CLK_PLL1_D8 9
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#define CLK_PLL1_D11 10
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#define CLK_PLL1_D13 11
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#define CLK_PLL1_D23 12
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#define CLK_PLL1_D64 13
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#define CLK_PLL1_D10_AUD 14
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#define CLK_PLL1_D100_AUD 15
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#define CLK_PLL2_D1 16
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#define CLK_PLL2_D2 17
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#define CLK_PLL2_D3 18
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#define CLK_PLL2_D4 19
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#define CLK_PLL2_D5 20
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#define CLK_PLL2_D6 21
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#define CLK_PLL2_D7 22
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#define CLK_PLL2_D8 23
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#define CLK_PLL3_D1 24
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#define CLK_PLL3_D2 25
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#define CLK_PLL3_D3 26
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#define CLK_PLL3_D4 27
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#define CLK_PLL3_D5 28
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#define CLK_PLL3_D6 29
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#define CLK_PLL3_D7 30
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#define CLK_PLL3_D8 31
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#define CLK_PLL3_80 32
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#define CLK_PLL3_40 33
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#define CLK_PLL3_20 34
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/* MPMU clocks */
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#define CLK_PLL1_307P2 0
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#define CLK_PLL1_76P8 1
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#define CLK_PLL1_61P44 2
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#define CLK_PLL1_153P6 3
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#define CLK_PLL1_102P4 4
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#define CLK_PLL1_51P2 5
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#define CLK_PLL1_51P2_AP 6
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#define CLK_PLL1_57P6 7
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#define CLK_PLL1_25P6 8
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#define CLK_PLL1_12P8 9
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#define CLK_PLL1_12P8_WDT 10
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#define CLK_PLL1_6P4 11
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#define CLK_PLL1_3P2 12
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#define CLK_PLL1_1P6 13
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#define CLK_PLL1_0P8 14
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#define CLK_PLL1_409P6 15
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#define CLK_PLL1_204P8 16
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#define CLK_PLL1_491 17
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#define CLK_PLL1_245P76 18
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#define CLK_PLL1_614 19
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#define CLK_PLL1_47P26 20
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#define CLK_PLL1_31P5 21
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#define CLK_PLL1_819 22
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#define CLK_PLL1_1228 23
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#define CLK_SLOW_UART 24
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#define CLK_SLOW_UART1 25
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#define CLK_SLOW_UART2 26
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#define CLK_WDT 27
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#define CLK_RIPC 28
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#define CLK_I2S_SYSCLK 29
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#define CLK_I2S_BCLK 30
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#define CLK_APB 31
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#define CLK_WDT_BUS 32
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/* APBC clocks */
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#define CLK_UART0 0
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#define CLK_UART2 1
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#define CLK_UART3 2
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#define CLK_UART4 3
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#define CLK_UART5 4
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#define CLK_UART6 5
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#define CLK_UART7 6
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#define CLK_UART8 7
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#define CLK_UART9 8
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#define CLK_GPIO 9
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#define CLK_PWM0 10
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#define CLK_PWM1 11
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#define CLK_PWM2 12
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#define CLK_PWM3 13
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#define CLK_PWM4 14
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#define CLK_PWM5 15
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#define CLK_PWM6 16
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#define CLK_PWM7 17
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#define CLK_PWM8 18
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#define CLK_PWM9 19
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#define CLK_PWM10 20
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#define CLK_PWM11 21
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#define CLK_PWM12 22
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#define CLK_PWM13 23
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#define CLK_PWM14 24
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#define CLK_PWM15 25
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#define CLK_PWM16 26
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#define CLK_PWM17 27
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#define CLK_PWM18 28
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#define CLK_PWM19 29
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#define CLK_SSP3 30
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#define CLK_RTC 31
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#define CLK_TWSI0 32
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#define CLK_TWSI1 33
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#define CLK_TWSI2 34
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#define CLK_TWSI4 35
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#define CLK_TWSI5 36
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#define CLK_TWSI6 37
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#define CLK_TWSI7 38
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#define CLK_TWSI8 39
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#define CLK_TIMERS1 40
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#define CLK_TIMERS2 41
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#define CLK_AIB 42
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#define CLK_ONEWIRE 43
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#define CLK_SSPA0 44
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#define CLK_SSPA1 45
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#define CLK_DRO 46
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#define CLK_IR 47
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#define CLK_TSEN 48
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#define CLK_IPC_AP2AUD 49
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#define CLK_CAN0 50
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#define CLK_CAN0_BUS 51
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#define CLK_UART0_BUS 52
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#define CLK_UART2_BUS 53
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#define CLK_UART3_BUS 54
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#define CLK_UART4_BUS 55
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#define CLK_UART5_BUS 56
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#define CLK_UART6_BUS 57
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#define CLK_UART7_BUS 58
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#define CLK_UART8_BUS 59
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#define CLK_UART9_BUS 60
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#define CLK_GPIO_BUS 61
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#define CLK_PWM0_BUS 62
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#define CLK_PWM1_BUS 63
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#define CLK_PWM2_BUS 64
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#define CLK_PWM3_BUS 65
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#define CLK_PWM4_BUS 66
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#define CLK_PWM5_BUS 67
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#define CLK_PWM6_BUS 68
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#define CLK_PWM7_BUS 69
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#define CLK_PWM8_BUS 70
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#define CLK_PWM9_BUS 71
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#define CLK_PWM10_BUS 72
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#define CLK_PWM11_BUS 73
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#define CLK_PWM12_BUS 74
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#define CLK_PWM13_BUS 75
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#define CLK_PWM14_BUS 76
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#define CLK_PWM15_BUS 77
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#define CLK_PWM16_BUS 78
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#define CLK_PWM17_BUS 79
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#define CLK_PWM18_BUS 80
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#define CLK_PWM19_BUS 81
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#define CLK_SSP3_BUS 82
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#define CLK_RTC_BUS 83
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#define CLK_TWSI0_BUS 84
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#define CLK_TWSI1_BUS 85
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#define CLK_TWSI2_BUS 86
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#define CLK_TWSI4_BUS 87
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#define CLK_TWSI5_BUS 88
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#define CLK_TWSI6_BUS 89
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#define CLK_TWSI7_BUS 90
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#define CLK_TWSI8_BUS 91
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#define CLK_TIMERS1_BUS 92
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#define CLK_TIMERS2_BUS 93
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#define CLK_AIB_BUS 94
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#define CLK_ONEWIRE_BUS 95
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#define CLK_SSPA0_BUS 96
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#define CLK_SSPA1_BUS 97
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#define CLK_TSEN_BUS 98
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#define CLK_IPC_AP2AUD_BUS 99
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/* APMU clocks */
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#define CLK_CCI550 0
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#define CLK_CPU_C0_HI 1
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#define CLK_CPU_C0_CORE 2
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#define CLK_CPU_C0_ACE 3
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#define CLK_CPU_C0_TCM 4
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#define CLK_CPU_C1_HI 5
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#define CLK_CPU_C1_CORE 6
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#define CLK_CPU_C1_ACE 7
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#define CLK_CCIC_4X 8
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#define CLK_CCIC1PHY 9
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#define CLK_SDH_AXI 10
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#define CLK_SDH0 11
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#define CLK_SDH1 12
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#define CLK_SDH2 13
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#define CLK_USB_P1 14
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#define CLK_USB_AXI 15
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#define CLK_USB30 16
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#define CLK_QSPI 17
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#define CLK_QSPI_BUS 18
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#define CLK_DMA 19
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#define CLK_AES 20
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#define CLK_VPU 21
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#define CLK_GPU 22
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#define CLK_EMMC 23
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#define CLK_EMMC_X 24
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#define CLK_AUDIO 25
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#define CLK_HDMI 26
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#define CLK_PMUA_ACLK 27
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#define CLK_PCIE0_MASTER 28
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#define CLK_PCIE0_SLAVE 29
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#define CLK_PCIE0_DBI 30
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#define CLK_PCIE1_MASTER 31
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#define CLK_PCIE1_SLAVE 32
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#define CLK_PCIE1_DBI 33
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#define CLK_PCIE2_MASTER 34
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#define CLK_PCIE2_SLAVE 35
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#define CLK_PCIE2_DBI 36
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#define CLK_EMAC0_BUS 37
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#define CLK_EMAC0_PTP 38
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#define CLK_EMAC1_BUS 39
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#define CLK_EMAC1_PTP 40
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#define CLK_JPG 41
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#define CLK_CCIC2PHY 42
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#define CLK_CCIC3PHY 43
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#define CLK_CSI 44
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#define CLK_CAMM0 45
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#define CLK_CAMM1 46
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#define CLK_CAMM2 47
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#define CLK_ISP_CPP 48
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#define CLK_ISP_BUS 49
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#define CLK_ISP 50
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#define CLK_DPU_MCLK 51
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#define CLK_DPU_ESC 52
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#define CLK_DPU_BIT 53
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#define CLK_DPU_PXCLK 54
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#define CLK_DPU_HCLK 55
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#define CLK_DPU_SPI 56
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#define CLK_DPU_SPI_HBUS 57
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#define CLK_DPU_SPIBUS 58
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#define CLK_DPU_SPI_ACLK 59
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#define CLK_V2D 60
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#define CLK_EMMC_BUS 61
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#endif /* _DT_BINDINGS_SPACEMIT_CCU_H_ */
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