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Currently i915_gem_object_pin_to_display_plane() uses i915_gem_object_get_tile_row_size() to calculate the tile row size for the VT-d guard w/a. That's not really proper since i915_gem_object_get_tile_row_size() only works for fenced BOs, nor does it take rotation into account. Remedy the situation by calculating the VT-d guard size in the display code where we have more information readily available. Although the default guard size (168 PTEs now) should cover the more typical fb size use cases anyway, and only very large Y/Yf-tiled framebuffers might have tile row size that exceeds it. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20250122151755.6928-4-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
32 lines
796 B
C
32 lines
796 B
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2021 Intel Corporation
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*/
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#ifndef __INTEL_FB_PIN_H__
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#define __INTEL_FB_PIN_H__
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#include <linux/types.h>
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struct drm_framebuffer;
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struct i915_vma;
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struct intel_plane_state;
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struct i915_gtt_view;
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struct i915_vma *
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intel_fb_pin_to_ggtt(const struct drm_framebuffer *fb,
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const struct i915_gtt_view *view,
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unsigned int alignment,
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unsigned int phys_alignment,
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unsigned int vtd_guard,
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bool uses_fence,
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unsigned long *out_flags);
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void intel_fb_unpin_vma(struct i915_vma *vma, unsigned long flags);
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int intel_plane_pin_fb(struct intel_plane_state *new_plane_state,
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const struct intel_plane_state *old_plane_state);
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void intel_plane_unpin_fb(struct intel_plane_state *old_plane_state);
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#endif
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