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bf85319903
The dedicated display PHYs reset to a power state that blocks S0ix,
increasing idle system power. After a system reset (cold boot,
S3/4/5, warm reset) if a dedicated PHY is not being brought up
shortly, use these steps to move the PHY to the lowest power state
to save power.
1. Follow the PLL Enable Sequence, using any valid frequency such
as DP 1.62 GHz. This brings lanes out of reset and enables the
PLL to allow powerdown to be moved to the Disable state.
2. Follow PLL Disable Sequence. This moves powerdown to the Disable
state and disables the PLL.
v2: Rename WA function to more descriptive (Jani)
For PTL, only port A needs this wa
Add helpers to check presence of C10 phy and pll enabling (Imre)
v3: Rename wa function (Imre)
Check return value of C10 pll tables readout (Imre)
Use PLL request to check pll enabling (Imre)
v4: Move intel_cx0_pll_is_enabled() right after
intel_cx0_pll_disable() (Imre)
Add drm_WARN_ON() if C10 state cannot be calculated from
the tables (Imre)
v5: Add debug message on PLL enabling (Imre)
Add check for intel_encoder_is_dig_port() (Imre)
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250218100019.740556-3-mika.kahola@intel.com
48 lines
1.6 KiB
C
48 lines
1.6 KiB
C
// SPDX-License-Identifier: MIT
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/*
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* Copyright © 2023 Intel Corporation
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*/
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#ifndef __INTEL_CX0_PHY_H__
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#define __INTEL_CX0_PHY_H__
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#include <linux/types.h>
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enum icl_port_dpll_id;
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struct intel_atomic_state;
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struct intel_c10pll_state;
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struct intel_c20pll_state;
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struct intel_crtc;
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struct intel_crtc_state;
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struct intel_cx0pll_state;
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struct intel_display;
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struct intel_encoder;
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struct intel_hdmi;
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bool intel_encoder_is_c10phy(struct intel_encoder *encoder);
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void intel_mtl_pll_enable(struct intel_encoder *encoder,
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const struct intel_crtc_state *crtc_state);
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void intel_mtl_pll_disable(struct intel_encoder *encoder);
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enum icl_port_dpll_id
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intel_mtl_port_pll_type(struct intel_encoder *encoder,
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const struct intel_crtc_state *crtc_state);
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int intel_cx0pll_calc_state(struct intel_crtc_state *crtc_state, struct intel_encoder *encoder);
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void intel_cx0pll_readout_hw_state(struct intel_encoder *encoder,
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struct intel_cx0pll_state *pll_state);
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int intel_cx0pll_calc_port_clock(struct intel_encoder *encoder,
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const struct intel_cx0pll_state *pll_state);
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void intel_cx0pll_dump_hw_state(struct intel_display *display,
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const struct intel_cx0pll_state *hw_state);
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void intel_cx0pll_state_verify(struct intel_atomic_state *state,
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struct intel_crtc *crtc);
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bool intel_cx0pll_compare_hw_state(const struct intel_cx0pll_state *a,
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const struct intel_cx0pll_state *b);
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void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder,
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const struct intel_crtc_state *crtc_state);
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int intel_mtl_tbt_calc_port_clock(struct intel_encoder *encoder);
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void intel_cx0_pll_power_save_wa(struct intel_display *display);
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#endif /* __INTEL_CX0_PHY_H__ */
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