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a958c7f13b
Add register constants for VGACR99 and use them when detecting the size of the VGA memory. Aligns the code with the programming manual. Also replace literal size values with Linux' SZ_ size constants. Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de> Reviewed-by: Jocelyn Falempe <jfalempe@redhat.com> Link: https://patchwork.freedesktop.org/patch/msgid/20250305163207.267650-4-tzimmermann@suse.de
78 lines
2.4 KiB
C
78 lines
2.4 KiB
C
/* SPDX-License-Identifier: MIT */
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#ifndef __AST_REG_H__
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#define __AST_REG_H__
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#include <linux/bits.h>
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/*
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* Modesetting
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*/
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#define AST_IO_MM_OFFSET (0x380)
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#define AST_IO_MM_LENGTH (128)
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#define AST_IO_VGAARI_W (0x40)
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#define AST_IO_VGAMR_W (0x42)
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#define AST_IO_VGAMR_R (0x4c)
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#define AST_IO_VGAMR_IOSEL BIT(0)
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#define AST_IO_VGAER (0x43)
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#define AST_IO_VGAER_VGA_ENABLE BIT(0)
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#define AST_IO_VGASRI (0x44)
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#define AST_IO_VGASR1_SD BIT(5)
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#define AST_IO_VGADRR (0x47)
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#define AST_IO_VGADWR (0x48)
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#define AST_IO_VGAPDR (0x49)
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#define AST_IO_VGAGRI (0x4E)
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#define AST_IO_VGACRI (0x54)
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#define AST_IO_VGACR80_PASSWORD (0xa8)
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#define AST_IO_VGACR99_VGAMEM_RSRV_MASK GENMASK(1, 0)
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#define AST_IO_VGACRA1_VGAIO_DISABLED BIT(1)
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#define AST_IO_VGACRA1_MMIO_ENABLED BIT(2)
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#define AST_IO_VGACRA3_DVO_ENABLED BIT(7)
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#define AST_IO_VGACRAA_VGAMEM_SIZE_MASK GENMASK(1, 0)
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#define AST_IO_VGACRB6_HSYNC_OFF BIT(0)
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#define AST_IO_VGACRB6_VSYNC_OFF BIT(1)
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#define AST_IO_VGACRCB_HWC_16BPP BIT(0) /* set: ARGB4444, cleared: 2bpp palette */
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#define AST_IO_VGACRCB_HWC_ENABLED BIT(1)
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/* mirrors SCU100[7:0] */
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#define AST_IO_VGACRD0_VRAM_INIT_STATUS_MASK GENMASK(7, 6)
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#define AST_IO_VGACRD0_VRAM_INIT_BY_BMC BIT(7)
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#define AST_IO_VGACRD0_VRAM_INIT_READY BIT(6)
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#define AST_IO_VGACRD0_IKVM_WIDESCREEN BIT(0)
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#define AST_IO_VGACRD1_MCU_FW_EXECUTING BIT(5)
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/* Display Transmitter Type */
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#define AST_IO_VGACRD1_TX_TYPE_MASK GENMASK(3, 1)
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#define AST_IO_VGACRD1_NO_TX 0x00
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#define AST_IO_VGACRD1_TX_ITE66121_VBIOS 0x02
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#define AST_IO_VGACRD1_TX_SIL164_VBIOS 0x04
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#define AST_IO_VGACRD1_TX_CH7003_VBIOS 0x06
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#define AST_IO_VGACRD1_TX_DP501_VBIOS 0x08
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#define AST_IO_VGACRD1_TX_ANX9807_VBIOS 0x0a
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#define AST_IO_VGACRD1_TX_FW_EMBEDDED_FW 0x0c /* special case of DP501 */
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#define AST_IO_VGACRD1_TX_ASTDP 0x0e
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#define AST_IO_VGACRD1_SUPPORTS_WUXGA BIT(0)
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/*
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* AST DisplayPort
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*/
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#define AST_IO_VGACRD7_EDID_VALID_FLAG BIT(0)
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#define AST_IO_VGACRDC_LINK_SUCCESS BIT(0)
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#define AST_IO_VGACRDF_HPD BIT(0)
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#define AST_IO_VGACRDF_DP_VIDEO_ENABLE BIT(4) /* mirrors AST_IO_VGACRE3_DP_VIDEO_ENABLE */
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#define AST_IO_VGACRE0_24BPP BIT(5) /* 18 bpp, if unset */
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#define AST_IO_VGACRE3_DP_VIDEO_ENABLE BIT(0)
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#define AST_IO_VGACRE3_DP_PHY_SLEEP BIT(4)
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#define AST_IO_VGACRE5_EDID_READ_DONE BIT(0)
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#define AST_IO_VGAIR1_R (0x5A)
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#define AST_IO_VGAIR1_VREFRESH BIT(3)
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#endif
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