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git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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ca4477e41c
Instead of providing crypto_shash algorithms for the arch-optimized SHA-256 code, instead implement the SHA-256 library. This is much simpler, it makes the SHA-256 library functions be arch-optimized, and it fixes the longstanding issue where the arch-optimized SHA-256 was disabled by default. SHA-256 still remains available through crypto_shash, but individual architectures no longer need to handle it. To merge the scalar, NEON, and CE code all into one module cleanly, add !CPU_V7M as a direct dependency of the CE code. Previously, !CPU_V7M was only a direct dependency of the scalar and NEON code. The result is still the same because CPU_V7M implies !KERNEL_MODE_NEON, so !CPU_V7M was already an indirect dependency of the CE code. To match sha256_blocks_arch(), change the type of the nblocks parameter of the assembly functions from int to size_t. The assembly functions actually already treated it as size_t. While renaming the assembly files, also fix the naming quirk where "sha2" meant sha256. (SHA-512 is also part of SHA-2.) Reviewed-by: Ard Biesheuvel <ardb@kernel.org> Signed-off-by: Eric Biggers <ebiggers@google.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
124 lines
2.7 KiB
ArmAsm
124 lines
2.7 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* sha256-ce.S - SHA-224/256 secure hash using ARMv8 Crypto Extensions
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*
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* Copyright (C) 2015 Linaro Ltd.
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* Author: Ard Biesheuvel <ard.biesheuvel@linaro.org>
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*/
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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.text
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.arch armv8-a
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.fpu crypto-neon-fp-armv8
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k0 .req q7
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k1 .req q8
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rk .req r3
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ta0 .req q9
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ta1 .req q10
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tb0 .req q10
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tb1 .req q9
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dga .req q11
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dgb .req q12
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dg0 .req q13
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dg1 .req q14
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dg2 .req q15
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.macro add_only, ev, s0
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vmov dg2, dg0
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.ifnb \s0
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vld1.32 {k\ev}, [rk, :128]!
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.endif
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sha256h.32 dg0, dg1, tb\ev
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sha256h2.32 dg1, dg2, tb\ev
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.ifnb \s0
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vadd.u32 ta\ev, q\s0, k\ev
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.endif
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.endm
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.macro add_update, ev, s0, s1, s2, s3
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sha256su0.32 q\s0, q\s1
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add_only \ev, \s1
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sha256su1.32 q\s0, q\s2, q\s3
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.endm
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.align 6
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.Lsha256_rcon:
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.word 0x428a2f98, 0x71374491, 0xb5c0fbcf, 0xe9b5dba5
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.word 0x3956c25b, 0x59f111f1, 0x923f82a4, 0xab1c5ed5
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.word 0xd807aa98, 0x12835b01, 0x243185be, 0x550c7dc3
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.word 0x72be5d74, 0x80deb1fe, 0x9bdc06a7, 0xc19bf174
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.word 0xe49b69c1, 0xefbe4786, 0x0fc19dc6, 0x240ca1cc
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.word 0x2de92c6f, 0x4a7484aa, 0x5cb0a9dc, 0x76f988da
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.word 0x983e5152, 0xa831c66d, 0xb00327c8, 0xbf597fc7
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.word 0xc6e00bf3, 0xd5a79147, 0x06ca6351, 0x14292967
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.word 0x27b70a85, 0x2e1b2138, 0x4d2c6dfc, 0x53380d13
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.word 0x650a7354, 0x766a0abb, 0x81c2c92e, 0x92722c85
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.word 0xa2bfe8a1, 0xa81a664b, 0xc24b8b70, 0xc76c51a3
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.word 0xd192e819, 0xd6990624, 0xf40e3585, 0x106aa070
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.word 0x19a4c116, 0x1e376c08, 0x2748774c, 0x34b0bcb5
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.word 0x391c0cb3, 0x4ed8aa4a, 0x5b9cca4f, 0x682e6ff3
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.word 0x748f82ee, 0x78a5636f, 0x84c87814, 0x8cc70208
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.word 0x90befffa, 0xa4506ceb, 0xbef9a3f7, 0xc67178f2
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/*
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* void sha256_ce_transform(u32 state[SHA256_STATE_WORDS],
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* const u8 *data, size_t nblocks);
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*/
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ENTRY(sha256_ce_transform)
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/* load state */
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vld1.32 {dga-dgb}, [r0]
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/* load input */
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0: vld1.32 {q0-q1}, [r1]!
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vld1.32 {q2-q3}, [r1]!
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subs r2, r2, #1
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#ifndef CONFIG_CPU_BIG_ENDIAN
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vrev32.8 q0, q0
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vrev32.8 q1, q1
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vrev32.8 q2, q2
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vrev32.8 q3, q3
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#endif
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/* load first round constant */
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adr rk, .Lsha256_rcon
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vld1.32 {k0}, [rk, :128]!
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vadd.u32 ta0, q0, k0
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vmov dg0, dga
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vmov dg1, dgb
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add_update 1, 0, 1, 2, 3
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add_update 0, 1, 2, 3, 0
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add_update 1, 2, 3, 0, 1
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add_update 0, 3, 0, 1, 2
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add_update 1, 0, 1, 2, 3
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add_update 0, 1, 2, 3, 0
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add_update 1, 2, 3, 0, 1
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add_update 0, 3, 0, 1, 2
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add_update 1, 0, 1, 2, 3
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add_update 0, 1, 2, 3, 0
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add_update 1, 2, 3, 0, 1
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add_update 0, 3, 0, 1, 2
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add_only 1, 1
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add_only 0, 2
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add_only 1, 3
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add_only 0
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/* update state */
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vadd.u32 dga, dga, dg0
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vadd.u32 dgb, dgb, dg1
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bne 0b
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/* store new state */
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vst1.32 {dga-dgb}, [r0]
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bx lr
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ENDPROC(sha256_ce_transform)
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