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f7380bba42
The NXP SJA1110 switch integrates its own, non-Synopsys PMA, but it manages it through the register space of the XPCS itself, in a small register window inside MDIO_MMD_VEND2 from address 0x8030 to 0x806e. This coincides with where the registers for the default Synopsys PMA are, but the register definitions are of course not the same. This situation is an odd hardware quirk, but the simplest way to manage it is to drive the SJA1110's PMA from within the XPCS driver. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Signed-off-by: David S. Miller <davem@davemloft.net>
116 lines
3.7 KiB
C
116 lines
3.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2020 Synopsys, Inc. and/or its affiliates.
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* Synopsys DesignWare XPCS helpers
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*
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* Author: Jose Abreu <Jose.Abreu@synopsys.com>
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*/
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#define SYNOPSYS_XPCS_ID 0x7996ced0
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#define SYNOPSYS_XPCS_MASK 0xffffffff
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/* Vendor regs access */
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#define DW_VENDOR BIT(15)
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/* VR_XS_PCS */
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#define DW_USXGMII_RST BIT(10)
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#define DW_USXGMII_EN BIT(9)
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#define DW_VR_XS_PCS_DIG_STS 0x0010
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#define DW_RXFIFO_ERR GENMASK(6, 5)
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/* SR_MII */
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#define DW_USXGMII_FULL BIT(8)
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#define DW_USXGMII_SS_MASK (BIT(13) | BIT(6) | BIT(5))
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#define DW_USXGMII_10000 (BIT(13) | BIT(6))
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#define DW_USXGMII_5000 (BIT(13) | BIT(5))
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#define DW_USXGMII_2500 (BIT(5))
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#define DW_USXGMII_1000 (BIT(6))
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#define DW_USXGMII_100 (BIT(13))
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#define DW_USXGMII_10 (0)
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/* SR_AN */
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#define DW_SR_AN_ADV1 0x10
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#define DW_SR_AN_ADV2 0x11
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#define DW_SR_AN_ADV3 0x12
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#define DW_SR_AN_LP_ABL1 0x13
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#define DW_SR_AN_LP_ABL2 0x14
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#define DW_SR_AN_LP_ABL3 0x15
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/* Clause 73 Defines */
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/* AN_LP_ABL1 */
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#define DW_C73_PAUSE BIT(10)
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#define DW_C73_ASYM_PAUSE BIT(11)
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#define DW_C73_AN_ADV_SF 0x1
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/* AN_LP_ABL2 */
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#define DW_C73_1000KX BIT(5)
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#define DW_C73_10000KX4 BIT(6)
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#define DW_C73_10000KR BIT(7)
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/* AN_LP_ABL3 */
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#define DW_C73_2500KX BIT(0)
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#define DW_C73_5000KR BIT(1)
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/* Clause 37 Defines */
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/* VR MII MMD registers offsets */
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#define DW_VR_MII_MMD_CTRL 0x0000
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#define DW_VR_MII_DIG_CTRL1 0x8000
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#define DW_VR_MII_AN_CTRL 0x8001
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#define DW_VR_MII_AN_INTR_STS 0x8002
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/* Enable 2.5G Mode */
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#define DW_VR_MII_DIG_CTRL1_2G5_EN BIT(2)
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/* EEE Mode Control Register */
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#define DW_VR_MII_EEE_MCTRL0 0x8006
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#define DW_VR_MII_EEE_MCTRL1 0x800b
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#define DW_VR_MII_DIG_CTRL2 0x80e1
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/* VR_MII_DIG_CTRL1 */
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#define DW_VR_MII_DIG_CTRL1_MAC_AUTO_SW BIT(9)
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/* VR_MII_DIG_CTRL2 */
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#define DW_VR_MII_DIG_CTRL2_TX_POL_INV BIT(4)
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#define DW_VR_MII_DIG_CTRL2_RX_POL_INV BIT(0)
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/* VR_MII_AN_CTRL */
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#define DW_VR_MII_AN_CTRL_TX_CONFIG_SHIFT 3
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#define DW_VR_MII_TX_CONFIG_MASK BIT(3)
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#define DW_VR_MII_TX_CONFIG_PHY_SIDE_SGMII 0x1
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#define DW_VR_MII_TX_CONFIG_MAC_SIDE_SGMII 0x0
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#define DW_VR_MII_AN_CTRL_PCS_MODE_SHIFT 1
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#define DW_VR_MII_PCS_MODE_MASK GENMASK(2, 1)
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#define DW_VR_MII_PCS_MODE_C37_1000BASEX 0x0
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#define DW_VR_MII_PCS_MODE_C37_SGMII 0x2
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/* VR_MII_AN_INTR_STS */
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#define DW_VR_MII_AN_STS_C37_ANSGM_FD BIT(1)
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#define DW_VR_MII_AN_STS_C37_ANSGM_SP_SHIFT 2
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#define DW_VR_MII_AN_STS_C37_ANSGM_SP GENMASK(3, 2)
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#define DW_VR_MII_C37_ANSGM_SP_10 0x0
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#define DW_VR_MII_C37_ANSGM_SP_100 0x1
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#define DW_VR_MII_C37_ANSGM_SP_1000 0x2
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#define DW_VR_MII_C37_ANSGM_SP_LNKSTS BIT(4)
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/* SR MII MMD Control defines */
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#define AN_CL37_EN BIT(12) /* Enable Clause 37 auto-nego */
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#define SGMII_SPEED_SS13 BIT(13) /* SGMII speed along with SS6 */
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#define SGMII_SPEED_SS6 BIT(6) /* SGMII speed along with SS13 */
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/* VR MII EEE Control 0 defines */
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#define DW_VR_MII_EEE_LTX_EN BIT(0) /* LPI Tx Enable */
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#define DW_VR_MII_EEE_LRX_EN BIT(1) /* LPI Rx Enable */
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#define DW_VR_MII_EEE_TX_QUIET_EN BIT(2) /* Tx Quiet Enable */
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#define DW_VR_MII_EEE_RX_QUIET_EN BIT(3) /* Rx Quiet Enable */
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#define DW_VR_MII_EEE_TX_EN_CTRL BIT(4) /* Tx Control Enable */
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#define DW_VR_MII_EEE_RX_EN_CTRL BIT(7) /* Rx Control Enable */
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#define DW_VR_MII_EEE_MULT_FACT_100NS_SHIFT 8
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#define DW_VR_MII_EEE_MULT_FACT_100NS GENMASK(11, 8)
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/* VR MII EEE Control 1 defines */
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#define DW_VR_MII_EEE_TRN_LPI BIT(0) /* Transparent Mode Enable */
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int xpcs_read(struct dw_xpcs *xpcs, int dev, u32 reg);
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int xpcs_write(struct dw_xpcs *xpcs, int dev, u32 reg, u16 val);
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int nxp_sja1105_sgmii_pma_config(struct dw_xpcs *xpcs);
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int nxp_sja1110_sgmii_pma_config(struct dw_xpcs *xpcs);
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int nxp_sja1110_2500basex_pma_config(struct dw_xpcs *xpcs);
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