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dd90451fac
Add the header, data structures and functions to populate the WQE descriptors and issue the Control QP commands that support RoCEv2 UD operations. Link: https://lore.kernel.org/r/20210602205138.889-11-shiraz.saleem@intel.com Signed-off-by: Mustafa Ismail <mustafa.ismail@intel.com> Signed-off-by: Shiraz Saleem <shiraz.saleem@intel.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
272 lines
8.2 KiB
C
272 lines
8.2 KiB
C
// SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB
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/* Copyright (c) 2016 - 2021 Intel Corporation */
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#include "osdep.h"
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#include "status.h"
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#include "hmc.h"
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#include "defs.h"
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#include "type.h"
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#include "protos.h"
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#include "uda.h"
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#include "uda_d.h"
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/**
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* irdma_sc_access_ah() - Create, modify or delete AH
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* @cqp: struct for cqp hw
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* @info: ah information
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* @op: Operation
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* @scratch: u64 saved to be used during cqp completion
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*/
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enum irdma_status_code irdma_sc_access_ah(struct irdma_sc_cqp *cqp,
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struct irdma_ah_info *info,
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u32 op, u64 scratch)
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{
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__le64 *wqe;
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u64 qw1, qw2;
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wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);
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if (!wqe)
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return IRDMA_ERR_RING_FULL;
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set_64bit_val(wqe, 0, ether_addr_to_u64(info->mac_addr) << 16);
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qw1 = FIELD_PREP(IRDMA_UDA_CQPSQ_MAV_PDINDEXLO, info->pd_idx) |
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FIELD_PREP(IRDMA_UDA_CQPSQ_MAV_TC, info->tc_tos) |
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FIELD_PREP(IRDMA_UDAQPC_VLANTAG, info->vlan_tag);
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qw2 = FIELD_PREP(IRDMA_UDA_CQPSQ_MAV_ARPINDEX, info->dst_arpindex) |
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FIELD_PREP(IRDMA_UDA_CQPSQ_MAV_FLOWLABEL, info->flow_label) |
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FIELD_PREP(IRDMA_UDA_CQPSQ_MAV_HOPLIMIT, info->hop_ttl) |
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FIELD_PREP(IRDMA_UDA_CQPSQ_MAV_PDINDEXHI, info->pd_idx >> 16);
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if (!info->ipv4_valid) {
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set_64bit_val(wqe, 40,
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FIELD_PREP(IRDMA_UDA_CQPSQ_MAV_ADDR0, info->dest_ip_addr[0]) |
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FIELD_PREP(IRDMA_UDA_CQPSQ_MAV_ADDR1, info->dest_ip_addr[1]));
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set_64bit_val(wqe, 32,
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FIELD_PREP(IRDMA_UDA_CQPSQ_MAV_ADDR2, info->dest_ip_addr[2]) |
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FIELD_PREP(IRDMA_UDA_CQPSQ_MAV_ADDR3, info->dest_ip_addr[3]));
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set_64bit_val(wqe, 56,
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FIELD_PREP(IRDMA_UDA_CQPSQ_MAV_ADDR0, info->src_ip_addr[0]) |
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FIELD_PREP(IRDMA_UDA_CQPSQ_MAV_ADDR1, info->src_ip_addr[1]));
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set_64bit_val(wqe, 48,
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FIELD_PREP(IRDMA_UDA_CQPSQ_MAV_ADDR2, info->src_ip_addr[2]) |
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FIELD_PREP(IRDMA_UDA_CQPSQ_MAV_ADDR3, info->src_ip_addr[3]));
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} else {
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set_64bit_val(wqe, 32,
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FIELD_PREP(IRDMA_UDA_CQPSQ_MAV_ADDR3, info->dest_ip_addr[0]));
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set_64bit_val(wqe, 48,
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FIELD_PREP(IRDMA_UDA_CQPSQ_MAV_ADDR3, info->src_ip_addr[0]));
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}
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set_64bit_val(wqe, 8, qw1);
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set_64bit_val(wqe, 16, qw2);
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dma_wmb(); /* need write block before writing WQE header */
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set_64bit_val(
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wqe, 24,
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FIELD_PREP(IRDMA_UDA_CQPSQ_MAV_WQEVALID, cqp->polarity) |
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FIELD_PREP(IRDMA_UDA_CQPSQ_MAV_OPCODE, op) |
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FIELD_PREP(IRDMA_UDA_CQPSQ_MAV_DOLOOPBACKK, info->do_lpbk) |
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FIELD_PREP(IRDMA_UDA_CQPSQ_MAV_IPV4VALID, info->ipv4_valid) |
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FIELD_PREP(IRDMA_UDA_CQPSQ_MAV_AVIDX, info->ah_idx) |
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FIELD_PREP(IRDMA_UDA_CQPSQ_MAV_INSERTVLANTAG, info->insert_vlan_tag));
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print_hex_dump_debug("WQE: MANAGE_AH WQE", DUMP_PREFIX_OFFSET, 16, 8,
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wqe, IRDMA_CQP_WQE_SIZE * 8, false);
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irdma_sc_cqp_post_sq(cqp);
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return 0;
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}
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/**
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* irdma_create_mg_ctx() - create a mcg context
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* @info: multicast group context info
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*/
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static enum irdma_status_code
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irdma_create_mg_ctx(struct irdma_mcast_grp_info *info)
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{
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struct irdma_mcast_grp_ctx_entry_info *entry_info = NULL;
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u8 idx = 0; /* index in the array */
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u8 ctx_idx = 0; /* index in the MG context */
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memset(info->dma_mem_mc.va, 0, IRDMA_MAX_MGS_PER_CTX * sizeof(u64));
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for (idx = 0; idx < IRDMA_MAX_MGS_PER_CTX; idx++) {
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entry_info = &info->mg_ctx_info[idx];
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if (entry_info->valid_entry) {
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set_64bit_val((__le64 *)info->dma_mem_mc.va,
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ctx_idx * sizeof(u64),
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FIELD_PREP(IRDMA_UDA_MGCTX_DESTPORT, entry_info->dest_port) |
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FIELD_PREP(IRDMA_UDA_MGCTX_VALIDENT, entry_info->valid_entry) |
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FIELD_PREP(IRDMA_UDA_MGCTX_QPID, entry_info->qp_id));
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ctx_idx++;
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}
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}
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return 0;
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}
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/**
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* irdma_access_mcast_grp() - Access mcast group based on op
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* @cqp: Control QP
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* @info: multicast group context info
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* @op: operation to perform
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* @scratch: u64 saved to be used during cqp completion
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*/
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enum irdma_status_code irdma_access_mcast_grp(struct irdma_sc_cqp *cqp,
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struct irdma_mcast_grp_info *info,
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u32 op, u64 scratch)
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{
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__le64 *wqe;
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enum irdma_status_code ret_code = 0;
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if (info->mg_id >= IRDMA_UDA_MAX_FSI_MGS) {
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ibdev_dbg(to_ibdev(cqp->dev), "WQE: mg_id out of range\n");
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return IRDMA_ERR_PARAM;
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}
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wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);
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if (!wqe) {
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ibdev_dbg(to_ibdev(cqp->dev), "WQE: ring full\n");
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return IRDMA_ERR_RING_FULL;
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}
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ret_code = irdma_create_mg_ctx(info);
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if (ret_code)
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return ret_code;
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set_64bit_val(wqe, 32, info->dma_mem_mc.pa);
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set_64bit_val(wqe, 16,
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FIELD_PREP(IRDMA_UDA_CQPSQ_MG_VLANID, info->vlan_id) |
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FIELD_PREP(IRDMA_UDA_CQPSQ_QS_HANDLE, info->qs_handle));
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set_64bit_val(wqe, 0, ether_addr_to_u64(info->dest_mac_addr));
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set_64bit_val(wqe, 8,
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FIELD_PREP(IRDMA_UDA_CQPSQ_MG_HMC_FCN_ID, info->hmc_fcn_id));
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if (!info->ipv4_valid) {
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set_64bit_val(wqe, 56,
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FIELD_PREP(IRDMA_UDA_CQPSQ_MAV_ADDR0, info->dest_ip_addr[0]) |
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FIELD_PREP(IRDMA_UDA_CQPSQ_MAV_ADDR1, info->dest_ip_addr[1]));
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set_64bit_val(wqe, 48,
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FIELD_PREP(IRDMA_UDA_CQPSQ_MAV_ADDR2, info->dest_ip_addr[2]) |
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FIELD_PREP(IRDMA_UDA_CQPSQ_MAV_ADDR3, info->dest_ip_addr[3]));
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} else {
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set_64bit_val(wqe, 48,
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FIELD_PREP(IRDMA_UDA_CQPSQ_MAV_ADDR3, info->dest_ip_addr[0]));
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}
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dma_wmb(); /* need write memory block before writing the WQE header. */
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set_64bit_val(wqe, 24,
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FIELD_PREP(IRDMA_UDA_CQPSQ_MG_WQEVALID, cqp->polarity) |
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FIELD_PREP(IRDMA_UDA_CQPSQ_MG_OPCODE, op) |
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FIELD_PREP(IRDMA_UDA_CQPSQ_MG_MGIDX, info->mg_id) |
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FIELD_PREP(IRDMA_UDA_CQPSQ_MG_VLANVALID, info->vlan_valid) |
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FIELD_PREP(IRDMA_UDA_CQPSQ_MG_IPV4VALID, info->ipv4_valid));
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print_hex_dump_debug("WQE: MANAGE_MCG WQE", DUMP_PREFIX_OFFSET, 16, 8,
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wqe, IRDMA_CQP_WQE_SIZE * 8, false);
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print_hex_dump_debug("WQE: MCG_HOST CTX WQE", DUMP_PREFIX_OFFSET, 16,
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8, info->dma_mem_mc.va,
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IRDMA_MAX_MGS_PER_CTX * 8, false);
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irdma_sc_cqp_post_sq(cqp);
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return 0;
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}
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/**
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* irdma_compare_mgs - Compares two multicast group structures
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* @entry1: Multcast group info
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* @entry2: Multcast group info in context
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*/
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static bool irdma_compare_mgs(struct irdma_mcast_grp_ctx_entry_info *entry1,
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struct irdma_mcast_grp_ctx_entry_info *entry2)
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{
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if (entry1->dest_port == entry2->dest_port &&
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entry1->qp_id == entry2->qp_id)
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return true;
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return false;
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}
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/**
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* irdma_sc_add_mcast_grp - Allocates mcast group entry in ctx
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* @ctx: Multcast group context
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* @mg: Multcast group info
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*/
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enum irdma_status_code irdma_sc_add_mcast_grp(struct irdma_mcast_grp_info *ctx,
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struct irdma_mcast_grp_ctx_entry_info *mg)
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{
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u32 idx;
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bool free_entry_found = false;
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u32 free_entry_idx = 0;
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/* find either an identical or a free entry for a multicast group */
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for (idx = 0; idx < IRDMA_MAX_MGS_PER_CTX; idx++) {
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if (ctx->mg_ctx_info[idx].valid_entry) {
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if (irdma_compare_mgs(&ctx->mg_ctx_info[idx], mg)) {
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ctx->mg_ctx_info[idx].use_cnt++;
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return 0;
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}
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continue;
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}
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if (!free_entry_found) {
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free_entry_found = true;
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free_entry_idx = idx;
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}
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}
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if (free_entry_found) {
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ctx->mg_ctx_info[free_entry_idx] = *mg;
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ctx->mg_ctx_info[free_entry_idx].valid_entry = true;
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ctx->mg_ctx_info[free_entry_idx].use_cnt = 1;
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ctx->no_of_mgs++;
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return 0;
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}
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return IRDMA_ERR_NO_MEMORY;
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}
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/**
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* irdma_sc_del_mcast_grp - Delete mcast group
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* @ctx: Multcast group context
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* @mg: Multcast group info
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*
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* Finds and removes a specific mulicast group from context, all
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* parameters must match to remove a multicast group.
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*/
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enum irdma_status_code irdma_sc_del_mcast_grp(struct irdma_mcast_grp_info *ctx,
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struct irdma_mcast_grp_ctx_entry_info *mg)
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{
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u32 idx;
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/* find an entry in multicast group context */
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for (idx = 0; idx < IRDMA_MAX_MGS_PER_CTX; idx++) {
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if (!ctx->mg_ctx_info[idx].valid_entry)
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continue;
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if (irdma_compare_mgs(mg, &ctx->mg_ctx_info[idx])) {
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ctx->mg_ctx_info[idx].use_cnt--;
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if (!ctx->mg_ctx_info[idx].use_cnt) {
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ctx->mg_ctx_info[idx].valid_entry = false;
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ctx->no_of_mgs--;
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/* Remove gap if element was not the last */
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if (idx != ctx->no_of_mgs &&
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ctx->no_of_mgs > 0) {
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memcpy(&ctx->mg_ctx_info[idx],
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&ctx->mg_ctx_info[ctx->no_of_mgs - 1],
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sizeof(ctx->mg_ctx_info[idx]));
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ctx->mg_ctx_info[ctx->no_of_mgs - 1].valid_entry = false;
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}
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}
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return 0;
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}
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}
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return IRDMA_ERR_PARAM;
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}
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