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git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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20279628bb
- Check only PCIE_LINKUP, not LTSSM status, to determine whether the link is up (Shawn Lin) - Increase N_FTS (used in L0s->L0 transitions) and enable ASPM L0s for Root Complex and Endpoint modes (Shawn Lin) - Hide the broken ATS Capability in rockchip_pcie_ep_init() instead of rockchip_pcie_ep_pre_init() so it stays hidden after PERST# resets non-sticky registers (Shawn Lin) - Remove unused PCIE_CLIENT_GENERAL_DEBUG definition (Hans Zhang) - Organize register and bitfield definitions logically (Hans Zhang) - Use rockchip_pcie_link_up() to check link up instead of open coding, and use GENMASK() and FIELD_GET() when possible (Hans Zhang) - Call phy_power_off() before phy_exit() in rockchip_pcie_phy_deinit() (Diederik de Haas) - Return bool (not int) for link-up check in dw_pcie_ops.link_up() and armada8k, dra7xx, dw-rockchip, exynos, histb, keembay, keystone, kirin, meson, qcom, qcom-ep, rcar_gen4, spear13xx, tegra194, uniphier, visconti (Hans Zhang) - Return bool (not int) for link-up check in mobiveil_pab_ops.link_up() and layerscape-gen4, mobiveil (Hans Zhang) - Simplify j721e link-up check (Hans Zhang) - Convert pci-host-common to a library so platforms that don't need native host controller drivers don't need to include these helper functions (Manivannan Sadhasivam) * pci/controller/dw-rockchip: PCI: qcom: Replace PERST# sleep time with proper macro PCI: dw-rockchip: Replace PERST# sleep time with proper macro PCI: host-common: Convert to library for host controller drivers PCI: cadence: Simplify J721e link status check PCI: mobiveil: Return bool from link up check PCI: dwc: Return bool from link up check PCI: dw-rockchip: Fix PHY function call sequence in rockchip_pcie_phy_deinit() PCI: dw-rockchip: Use rockchip_pcie_link_up() to check link up instead of open coding PCI: dw-rockchip: Reorganize register and bitfield definitions PCI: dw-rockchip: Remove unused PCIE_CLIENT_GENERAL_DEBUG definition PCI: dw-rockchip: Move rockchip_pcie_ep_hide_broken_ats_cap_rk3588() to dw_pcie_ep_ops::init() PCI: dw-rockchip: Enable ASPM L0s capability for both RC and EP modes PCI: dw-rockchip: Remove PCIE_L0S_ENTRY check from rockchip_pcie_link_up() # Conflicts: # drivers/pci/controller/pcie-apple.c # include/linux/pci-ecam.h
109 lines
2.5 KiB
C
109 lines
2.5 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Common library for PCI host controller drivers
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*
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* Copyright (C) 2014 ARM Limited
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*
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* Author: Will Deacon <will.deacon@arm.com>
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_pci.h>
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#include <linux/pci-ecam.h>
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#include <linux/platform_device.h>
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#include "pci-host-common.h"
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static void gen_pci_unmap_cfg(void *ptr)
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{
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pci_ecam_free((struct pci_config_window *)ptr);
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}
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static struct pci_config_window *gen_pci_init(struct device *dev,
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struct pci_host_bridge *bridge, const struct pci_ecam_ops *ops)
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{
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int err;
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struct resource cfgres;
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struct resource_entry *bus;
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struct pci_config_window *cfg;
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err = of_address_to_resource(dev->of_node, 0, &cfgres);
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if (err) {
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dev_err(dev, "missing \"reg\" property\n");
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return ERR_PTR(err);
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}
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bus = resource_list_first_type(&bridge->windows, IORESOURCE_BUS);
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if (!bus)
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return ERR_PTR(-ENODEV);
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cfg = pci_ecam_create(dev, &cfgres, bus->res, ops);
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if (IS_ERR(cfg))
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return cfg;
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err = devm_add_action_or_reset(dev, gen_pci_unmap_cfg, cfg);
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if (err)
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return ERR_PTR(err);
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return cfg;
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}
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int pci_host_common_init(struct platform_device *pdev,
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const struct pci_ecam_ops *ops)
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{
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struct device *dev = &pdev->dev;
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struct pci_host_bridge *bridge;
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struct pci_config_window *cfg;
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bridge = devm_pci_alloc_host_bridge(dev, 0);
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if (!bridge)
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return -ENOMEM;
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of_pci_check_probe_only();
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/* Parse and map our Configuration Space windows */
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cfg = gen_pci_init(dev, bridge, ops);
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if (IS_ERR(cfg))
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return PTR_ERR(cfg);
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platform_set_drvdata(pdev, bridge);
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bridge->sysdata = cfg;
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bridge->ops = (struct pci_ops *)&ops->pci_ops;
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bridge->enable_device = ops->enable_device;
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bridge->disable_device = ops->disable_device;
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bridge->msi_domain = true;
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return pci_host_probe(bridge);
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}
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EXPORT_SYMBOL_GPL(pci_host_common_init);
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int pci_host_common_probe(struct platform_device *pdev)
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{
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const struct pci_ecam_ops *ops;
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ops = of_device_get_match_data(&pdev->dev);
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if (!ops)
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return -ENODEV;
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return pci_host_common_init(pdev, ops);
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}
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EXPORT_SYMBOL_GPL(pci_host_common_probe);
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void pci_host_common_remove(struct platform_device *pdev)
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{
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struct pci_host_bridge *bridge = platform_get_drvdata(pdev);
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pci_lock_rescan_remove();
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pci_stop_root_bus(bridge->bus);
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pci_remove_root_bus(bridge->bus);
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pci_unlock_rescan_remove();
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}
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EXPORT_SYMBOL_GPL(pci_host_common_remove);
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MODULE_DESCRIPTION("Common library for PCI host controller drivers");
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MODULE_LICENSE("GPL v2");
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