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7a92fc8b4d
The pcpu setup when using the page allocator sets up a new vmalloc mapping very early in the boot process, so early that it cannot use the flush_cache_vmap() function which may depend on structures not yet initialized (for example in riscv, we currently send an IPI to flush other cpus TLB). But on some architectures, we must call flush_cache_vmap(): for example, in riscv, some uarchs can cache invalid TLB entries so we need to flush the new established mapping to avoid taking an exception. So fix this by introducing a new function flush_cache_vmap_early() which is called right after setting the new page table entry and before accessing this new mapping. This new function implements a local flush tlb on riscv and is no-op for other architectures (same as today). Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com> Acked-by: Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: Dennis Zhou <dennis@kernel.org>
113 lines
3.6 KiB
C
113 lines
3.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
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*
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* vineetg: May 2011: for Non-aliasing VIPT D-cache following can be NOPs
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* -flush_cache_dup_mm (fork)
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* -likewise for flush_cache_mm (exit/execve)
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* -likewise for flush_cache_{range,page} (munmap, exit, COW-break)
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*
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* vineetg: April 2008
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* -Added a critical CacheLine flush to copy_to_user_page( ) which
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* was causing gdbserver to not setup breakpoints consistently
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*/
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#ifndef _ASM_CACHEFLUSH_H
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#define _ASM_CACHEFLUSH_H
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#include <linux/mm.h>
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#include <asm/shmparam.h>
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void flush_cache_all(void);
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void flush_icache_range(unsigned long kstart, unsigned long kend);
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void __sync_icache_dcache(phys_addr_t paddr, unsigned long vaddr, int len);
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void __inv_icache_pages(phys_addr_t paddr, unsigned long vaddr, unsigned nr);
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void __flush_dcache_pages(phys_addr_t paddr, unsigned long vaddr, unsigned nr);
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#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
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void flush_dcache_page(struct page *page);
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void flush_dcache_folio(struct folio *folio);
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#define flush_dcache_folio flush_dcache_folio
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void dma_cache_wback_inv(phys_addr_t start, unsigned long sz);
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void dma_cache_inv(phys_addr_t start, unsigned long sz);
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void dma_cache_wback(phys_addr_t start, unsigned long sz);
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#define flush_dcache_mmap_lock(mapping) do { } while (0)
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#define flush_dcache_mmap_unlock(mapping) do { } while (0)
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/* TBD: optimize this */
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#define flush_cache_vmap(start, end) flush_cache_all()
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#define flush_cache_vmap_early(start, end) do { } while (0)
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#define flush_cache_vunmap(start, end) flush_cache_all()
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#define flush_cache_dup_mm(mm) /* called on fork (VIVT only) */
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#ifndef CONFIG_ARC_CACHE_VIPT_ALIASING
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#define flush_cache_mm(mm) /* called on munmap/exit */
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#define flush_cache_range(mm, u_vstart, u_vend)
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#define flush_cache_page(vma, u_vaddr, pfn) /* PF handling/COW-break */
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#else /* VIPT aliasing dcache */
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/* To clear out stale userspace mappings */
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void flush_cache_mm(struct mm_struct *mm);
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void flush_cache_range(struct vm_area_struct *vma,
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unsigned long start,unsigned long end);
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void flush_cache_page(struct vm_area_struct *vma,
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unsigned long user_addr, unsigned long page);
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/*
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* To make sure that userspace mapping is flushed to memory before
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* get_user_pages() uses a kernel mapping to access the page
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*/
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#define ARCH_HAS_FLUSH_ANON_PAGE
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void flush_anon_page(struct vm_area_struct *vma,
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struct page *page, unsigned long u_vaddr);
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#endif /* CONFIG_ARC_CACHE_VIPT_ALIASING */
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/*
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* A new pagecache page has PG_arch_1 clear - thus dcache dirty by default
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* This works around some PIO based drivers which don't call flush_dcache_page
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* to record that they dirtied the dcache
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*/
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#define PG_dc_clean PG_arch_1
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#define CACHE_COLORS_NUM 4
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#define CACHE_COLORS_MSK (CACHE_COLORS_NUM - 1)
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#define CACHE_COLOR(addr) (((unsigned long)(addr) >> (PAGE_SHIFT)) & CACHE_COLORS_MSK)
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/*
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* Simple wrapper over config option
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* Bootup code ensures that hardware matches kernel configuration
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*/
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static inline int cache_is_vipt_aliasing(void)
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{
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return IS_ENABLED(CONFIG_ARC_CACHE_VIPT_ALIASING);
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}
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/*
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* checks if two addresses (after page aligning) index into same cache set
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*/
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#define addr_not_cache_congruent(addr1, addr2) \
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({ \
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cache_is_vipt_aliasing() ? \
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(CACHE_COLOR(addr1) != CACHE_COLOR(addr2)) : 0; \
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})
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#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
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do { \
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memcpy(dst, src, len); \
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if (vma->vm_flags & VM_EXEC) \
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__sync_icache_dcache((unsigned long)(dst), vaddr, len); \
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} while (0)
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#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
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memcpy(dst, src, len); \
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#endif
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