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36d68f64c4
Krait CPUs have a handful of L2 cache controller registers that live behind a cp15 based indirection register. First you program the indirection register (l2cpselr) to point the L2 'window' register (l2cpdr) at what you want to read/write. Then you read/write the 'window' register to do what you want. The l2cpselr register is not banked per-cpu so we must lock around accesses to it to prevent other CPUs from re-pointing l2cpdr underneath us. Cc: Mark Rutland <mark.rutland@arm.com> Cc: Russell King <linux@arm.linux.org.uk> Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Sricharan R <sricharan@codeaurora.org> Tested-by: Craig Tatlor <ctatlor97@gmail.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org> |
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| .. | ||
| bL_switcher_dummy_if.c | ||
| bL_switcher.c | ||
| dmabounce.c | ||
| firmware.c | ||
| it8152.c | ||
| Kconfig | ||
| krait-l2-accessors.c | ||
| locomo.c | ||
| Makefile | ||
| mcpm_entry.c | ||
| mcpm_head.S | ||
| mcpm_platsmp.c | ||
| sa1111.c | ||
| scoop.c | ||
| secure_cntvoff.S | ||
| sharpsl_param.c | ||
| vlock.h | ||
| vlock.S | ||