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		27c766aaac
		
	
	
	
	
		
			
			Use the current logging styles. Make sure all output has a prefix. Add missing newlines. Remove now unnecessary PFX, NAME, and miscellaneous other #defines. Coalesce formats. Signed-off-by: Joe Perches <joe@perches.com> Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
		
			
				
	
	
		
			66 lines
		
	
	
		
			2.0 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			66 lines
		
	
	
		
			2.0 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
| /*
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|  *      Intel_SCU 0.2:  An Intel SCU IOH Based Watchdog Device
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|  *			for Intel part #(s):
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|  *				- AF82MP20 PCH
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|  *
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|  *      Copyright (C) 2009-2010 Intel Corporation. All rights reserved.
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|  *
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|  *      This program is free software; you can redistribute it and/or
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|  *      modify it under the terms of version 2 of the GNU General
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|  *      Public License as published by the Free Software Foundation.
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|  *
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|  *      This program is distributed in the hope that it will be
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|  *      useful, but WITHOUT ANY WARRANTY; without even the implied
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|  *      warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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|  *      PURPOSE.  See the GNU General Public License for more details.
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|  *      You should have received a copy of the GNU General Public
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|  *      License along with this program; if not, write to the Free
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|  *      Software Foundation, Inc., 59 Temple Place - Suite 330,
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|  *      Boston, MA  02111-1307, USA.
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|  *      The full GNU General Public License is included in this
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|  *      distribution in the file called COPYING.
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|  *
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|  */
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| 
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| #ifndef __INTEL_SCU_WATCHDOG_H
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| #define __INTEL_SCU_WATCHDOG_H
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| 
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| #define WDT_VER "0.3"
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| 
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| /* minimum time between interrupts */
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| #define MIN_TIME_CYCLE 1
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| 
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| /* Time from warning to reboot is 2 seconds */
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| #define DEFAULT_SOFT_TO_HARD_MARGIN 2
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| 
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| #define MAX_TIME 170
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| 
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| #define DEFAULT_TIME 5
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| 
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| #define MAX_SOFT_TO_HARD_MARGIN (MAX_TIME-MIN_TIME_CYCLE)
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| 
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| /* Ajustment to clock tick frequency to make timing come out right */
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| #define FREQ_ADJUSTMENT 8
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| 
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| struct intel_scu_watchdog_dev {
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| 	ulong driver_open;
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| 	ulong driver_closed;
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| 	u32 timer_started;
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| 	u32 timer_set;
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| 	u32 threshold;
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| 	u32 soft_threshold;
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| 	u32 __iomem *timer_load_count_addr;
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| 	u32 __iomem *timer_current_value_addr;
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| 	u32 __iomem *timer_control_addr;
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| 	u32 __iomem *timer_clear_interrupt_addr;
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| 	u32 __iomem *timer_interrupt_status_addr;
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| 	struct sfi_timer_table_entry *timer_tbl_ptr;
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| 	struct notifier_block intel_scu_notifier;
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| 	struct miscdevice miscdev;
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| };
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| 
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| extern int sfi_mtimer_num;
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| 
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| /* extern struct sfi_timer_table_entry *sfi_get_mtmr(int hint); */
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| #endif /* __INTEL_SCU_WATCHDOG_H */
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