ling.ma@intel.com 6ff4fd0567 drm/i915: Set SSC frequency for 8xx chips correctly ...

All 8xx class chips have the 66/48 split, not just 855.

Signed-off-by: Ma Ling <ling.ma@intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>

2009-07-01 11:20:44 -07:00

..

drm

drm/i915: Set SSC frequency for 8xx chips correctly

2009-07-01 11:20:44 -07:00

Makefile

drm: reorganise drm tree to be more future proof.

2008-07-14 10:45:01 +10:00