Vincent Chen 6d1a6f464e rseq/selftests: Add support for RISC-V ...

Add support for RISC-V in the rseq selftests, which covers both
64-bit and 32-bit ISA with little endian mode.

Signed-off-by: Vincent Chen <vincent.chen@sifive.com>
Tested-by: Eric Lin <eric.lin@sifive.com>
Reviewed-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>

2022-03-22 14:45:19 -07:00

..

cxl

cxl/test: Mock acpi_table_parse_cedt()

2021-11-15 11:03:00 -08:00

fault-injection

…

ktest

bootconfig/tracing/ktest: Update ktest example for boot-time tracing

2021-08-16 11:39:51 -04:00

kunit

kunit: tool: Default --jobs to number of CPUs

2021-12-15 16:44:55 -07:00

nvdimm

memremap: remove support for external pgmap refcounts

2021-12-04 12:46:09 -08:00

radix-tree

tools: Fix math.h breakage

2021-11-30 09:14:42 -08:00

scatterlist

Merge branch 'akpm' (patches from Andrew)

2021-09-03 10:08:28 -07:00

selftests

rseq/selftests: Add support for RISC-V

2022-03-22 14:45:19 -07:00

vsock

vsock_diag_test: remove free_sock_stat() call in test_no_sockets

2021-10-15 17:21:34 -07:00