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git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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a5408ec605
Add clocks/resets defines for the global clock controller found on Qualcomm MSM8916 SoCs. Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
109 lines
3.3 KiB
C
109 lines
3.3 KiB
C
/*
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* Copyright 2015 Linaro Limited
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _DT_BINDINGS_RESET_MSM_GCC_8916_H
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#define _DT_BINDINGS_RESET_MSM_GCC_8916_H
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#define GCC_BLSP1_BCR 0
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#define GCC_BLSP1_QUP1_BCR 1
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#define GCC_BLSP1_UART1_BCR 2
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#define GCC_BLSP1_QUP2_BCR 3
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#define GCC_BLSP1_UART2_BCR 4
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#define GCC_BLSP1_QUP3_BCR 5
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#define GCC_BLSP1_QUP4_BCR 6
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#define GCC_BLSP1_QUP5_BCR 7
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#define GCC_BLSP1_QUP6_BCR 8
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#define GCC_IMEM_BCR 9
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#define GCC_SMMU_BCR 10
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#define GCC_APSS_TCU_BCR 11
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#define GCC_SMMU_XPU_BCR 12
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#define GCC_PCNOC_TBU_BCR 13
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#define GCC_PRNG_BCR 14
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#define GCC_BOOT_ROM_BCR 15
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#define GCC_CRYPTO_BCR 16
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#define GCC_SEC_CTRL_BCR 17
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#define GCC_AUDIO_CORE_BCR 18
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#define GCC_ULT_AUDIO_BCR 19
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#define GCC_DEHR_BCR 20
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#define GCC_SYSTEM_NOC_BCR 21
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#define GCC_PCNOC_BCR 22
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#define GCC_TCSR_BCR 23
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#define GCC_QDSS_BCR 24
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#define GCC_DCD_BCR 25
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#define GCC_MSG_RAM_BCR 26
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#define GCC_MPM_BCR 27
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#define GCC_SPMI_BCR 28
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#define GCC_SPDM_BCR 29
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#define GCC_MM_SPDM_BCR 30
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#define GCC_BIMC_BCR 31
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#define GCC_RBCPR_BCR 32
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#define GCC_TLMM_BCR 33
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#define GCC_USB_HS_BCR 34
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#define GCC_USB2A_PHY_BCR 35
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#define GCC_SDCC1_BCR 36
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#define GCC_SDCC2_BCR 37
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#define GCC_PDM_BCR 38
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#define GCC_SNOC_BUS_TIMEOUT0_BCR 39
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#define GCC_PCNOC_BUS_TIMEOUT0_BCR 40
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#define GCC_PCNOC_BUS_TIMEOUT1_BCR 41
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#define GCC_PCNOC_BUS_TIMEOUT2_BCR 42
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#define GCC_PCNOC_BUS_TIMEOUT3_BCR 43
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#define GCC_PCNOC_BUS_TIMEOUT4_BCR 44
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#define GCC_PCNOC_BUS_TIMEOUT5_BCR 45
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#define GCC_PCNOC_BUS_TIMEOUT6_BCR 46
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#define GCC_PCNOC_BUS_TIMEOUT7_BCR 47
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#define GCC_PCNOC_BUS_TIMEOUT8_BCR 48
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#define GCC_PCNOC_BUS_TIMEOUT9_BCR 49
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#define GCC_MMSS_BCR 50
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#define GCC_VENUS0_BCR 51
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#define GCC_MDSS_BCR 52
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#define GCC_CAMSS_PHY0_BCR 53
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#define GCC_CAMSS_CSI0_BCR 54
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#define GCC_CAMSS_CSI0PHY_BCR 55
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#define GCC_CAMSS_CSI0RDI_BCR 56
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#define GCC_CAMSS_CSI0PIX_BCR 57
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#define GCC_CAMSS_PHY1_BCR 58
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#define GCC_CAMSS_CSI1_BCR 59
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#define GCC_CAMSS_CSI1PHY_BCR 60
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#define GCC_CAMSS_CSI1RDI_BCR 61
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#define GCC_CAMSS_CSI1PIX_BCR 62
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#define GCC_CAMSS_ISPIF_BCR 63
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#define GCC_CAMSS_CCI_BCR 64
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#define GCC_CAMSS_MCLK0_BCR 65
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#define GCC_CAMSS_MCLK1_BCR 66
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#define GCC_CAMSS_GP0_BCR 67
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#define GCC_CAMSS_GP1_BCR 68
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#define GCC_CAMSS_TOP_BCR 69
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#define GCC_CAMSS_MICRO_BCR 70
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#define GCC_CAMSS_JPEG_BCR 71
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#define GCC_CAMSS_VFE_BCR 72
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#define GCC_CAMSS_CSI_VFE0_BCR 73
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#define GCC_OXILI_BCR 74
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#define GCC_GMEM_BCR 75
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#define GCC_CAMSS_AHB_BCR 76
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#define GCC_MDP_TBU_BCR 77
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#define GCC_GFX_TBU_BCR 78
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#define GCC_GFX_TCU_BCR 79
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#define GCC_MSS_TBU_AXI_BCR 80
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#define GCC_MSS_TBU_GSS_AXI_BCR 81
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#define GCC_MSS_TBU_Q6_AXI_BCR 82
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#define GCC_GTCU_AHB_BCR 83
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#define GCC_SMMU_CFG_BCR 84
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#define GCC_VFE_TBU_BCR 85
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#define GCC_VENUS_TBU_BCR 86
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#define GCC_JPEG_TBU_BCR 87
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#define GCC_PRONTO_TBU_BCR 88
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#define GCC_SMMU_CATS_BCR 89
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#endif
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