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The maximum guardband value is constrained by two factors: - The actual vblank length minus set context latency (SCL) - The hardware register field width: - 8 bits for ICL/TGL (VRR_CTL_PIPELINE_FULL_MASK -> max 255) - 16 bits for ADL+ (XELPD_VRR_CTL_VRR_GUARDBAND_MASK -> max 65535) Remove the #FIXME and clamp the guardband to the maximum allowed value. v2: - Use REG_FIELD_MAX(). (Ville) - Separate out functions for intel_vrr_max_guardband(), intel_vrr_max_vblank_guardband(). (Ville) v3: - Fix Typo: Add the missing adjusted_mode->crtc_vdisplay in guardband computation. (Ville) - Refactor intel_vrr_max_hw_guardband() and use else for consistency. (Ville) v4: - Drop max_guardband from intel_vrr_max_hw_guardband(). (Ville) Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> (#v2) Link: https://lore.kernel.org/r/20250924141542.3122126-9-ankit.k.nautiyal@intel.com