Ben Skeggs 5e5a195ecc drm/nouveau/clock: fix missing pll type/addr when matching default entry ...

This issue is a regression from 70790f4f81,
and causes us to miss a special-case for C51 (NV4E) chipsets and return
the wrong reference frequency for the VPLLs.

Should fix fdo#56202

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

2012-10-22 14:38:06 +10:00

..

drm

drm/nouveau/clock: fix missing pll type/addr when matching default entry

2012-10-22 14:38:06 +10:00

stub

i915: select VIDEO_OUTPUT_CONTROL for ACPI_VIDEO

2011-04-13 09:10:25 +10:00

vga

vga_switcheroo: Don't require handler init callback

2012-08-17 17:34:41 -04:00

Makefile

gpu: Add Intel GMA500(Poulsbo) Stub Driver

2010-10-26 11:00:13 +10:00