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1100030022
The T820, G31 & G52 GPUs integrated by Amlogic in the respective GXM, G12A/SM1 & G12B SoCs needs a quirk in the PWR registers at the GPU reset time. Since the Amlogic's integration of the GPU cores with the SoC is not publicly documented we do not know what does these values, but they permit having a fully functional GPU running with Panfrost. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> [Steven: Fix typo in commit log] Reviewed-by: Steven Price <steven.price@arm.com> Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Signed-off-by: Steven Price <steven.price@arm.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200916150147.25753-3-narmstrong@baylibre.com
22 lines
651 B
C
22 lines
651 B
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright 2018 Marty E. Plummer <hanetzer@startmail.com> */
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/* Copyright 2019 Collabora ltd. */
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#ifndef __PANFROST_GPU_H__
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#define __PANFROST_GPU_H__
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struct panfrost_device;
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int panfrost_gpu_init(struct panfrost_device *pfdev);
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void panfrost_gpu_fini(struct panfrost_device *pfdev);
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u32 panfrost_gpu_get_latest_flush_id(struct panfrost_device *pfdev);
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int panfrost_gpu_soft_reset(struct panfrost_device *pfdev);
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void panfrost_gpu_power_on(struct panfrost_device *pfdev);
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void panfrost_gpu_power_off(struct panfrost_device *pfdev);
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void panfrost_gpu_amlogic_quirk(struct panfrost_device *pfdev);
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#endif
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