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2c50a570e9
This patch was triggered by a remark from Russell that
introducing a call to the waituart (needed to fix debug prints
on the Qualcomm platforms) was dangerous because in some cases
this will involve waiting for a modem CTS (clear to send)
signal, and debug messages would maybe not work on platforms
with no modem connected to the UART port: they will just
hang waiting for the modem to assert CTS and this might never
happen.
Looking through all UART debug drivers implementing the waituart
macro I discovered that all users except two actually use this
macro to check if the UART is ready for TX, let's call this
TXRDY.
Only two debug UART drivers actually check for CTS:
- arch/arm/include/debug/8250.S
- arch/arm/include/debug/tegra.S
The former is very significant since the 8250 is possibly
the most common UART on the planet.
We have the following problem: the semantics of waituart are
ambiguous making it dangerous to introduce the macro to debug
code fixing debug prints for Qualcomm. To start to pry this
problem apart, this patch does the following:
- Convert all debug UART drivers to define two macros:
- waituartcts with the clear semantic to wait for CTS
to be asserted
- waituarttxrdy with the clear semantic to wait for the TX
capability of the UART to be ready
- When doing this take care to assign the right function to
each drivers macro, so they now do exactly the above.
- Update the three sites in the kernel invoking the waituart
macro to call waituartcts/waituarttxrdy in sequence, so that
the functional impact on the kernel should be zero.
After this we can start to change the code sites using this
code to do the right thing.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
49 lines
1.0 KiB
ArmAsm
49 lines
1.0 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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*
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* Copyright (C) 2007 Google, Inc.
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* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
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* Author: Brian Swetland <swetland@google.com>
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*/
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.macro addruart, rp, rv, tmp
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ldr \rp, =CONFIG_DEBUG_UART_PHYS
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ldr \rv, =CONFIG_DEBUG_UART_VIRT
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.endm
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.macro senduart, rd, rx
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ARM_BE8(rev \rd, \rd )
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@ Write the 1 character to UARTDM_TF
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str \rd, [\rx, #0x70]
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.endm
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.macro waituartcts,rd,rx
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.endm
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.macro waituarttxrdy, rd, rx
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@ check for TX_EMT in UARTDM_SR
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ldr \rd, [\rx, #0x08]
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ARM_BE8(rev \rd, \rd )
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tst \rd, #0x08
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bne 1002f
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@ wait for TXREADY in UARTDM_ISR
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1001: ldr \rd, [\rx, #0x14]
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ARM_BE8(rev \rd, \rd )
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tst \rd, #0x80
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beq 1001b
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1002:
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@ Clear TX_READY by writing to the UARTDM_CR register
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mov \rd, #0x300
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ARM_BE8(rev \rd, \rd )
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str \rd, [\rx, #0x10]
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@ Write 0x1 to NCF register
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mov \rd, #0x1
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ARM_BE8(rev \rd, \rd )
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str \rd, [\rx, #0x40]
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@ UARTDM reg. Read to induce delay
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ldr \rd, [\rx, #0x08]
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.endm
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.macro busyuart, rd, rx
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.endm
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