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e96418da0a
The Documentation/DMA-API-HOWTO.txt states that the dma_map_sg() function
returns the number of the created entries in the DMA address space.
However the subsequent calls to the dma_sync_sg_for_{device,cpu}() and
dma_unmap_sg must be called with the original number of the entries
passed to the dma_map_sg().
struct sg_table is a common structure used for describing a non-contiguous
memory buffer, used commonly in the DRM and graphics subsystems. It
consists of a scatterlist with memory pages and DMA addresses (sgl entry),
as well as the number of scatterlist entries: CPU pages (orig_nents entry)
and DMA mapped pages (nents entry).
It turned out that it was a common mistake to misuse nents and orig_nents
entries, calling DMA-mapping functions with a wrong number of entries or
ignoring the number of mapped entries returned by the dma_map_sg()
function.
To avoid such issues, lets use a common dma-mapping wrappers operating
directly on the struct sg_table objects and use scatterlist page
iterators where possible. This, almost always, hides references to the
nents and orig_nents entries, making the code robust, easier to follow
and copy/paste safe.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
126 lines
3.5 KiB
C
126 lines
3.5 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/* Copyright (C) 2017-2018 Broadcom */
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/**
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* DOC: Broadcom V3D MMU
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*
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* The V3D 3.x hardware (compared to VC4) now includes an MMU. It has
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* a single level of page tables for the V3D's 4GB address space to
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* map to AXI bus addresses, thus it could need up to 4MB of
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* physically contiguous memory to store the PTEs.
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*
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* Because the 4MB of contiguous memory for page tables is precious,
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* and switching between them is expensive, we load all BOs into the
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* same 4GB address space.
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*
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* To protect clients from each other, we should use the GMP to
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* quickly mask out (at 128kb granularity) what pages are available to
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* each client. This is not yet implemented.
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*/
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#include "v3d_drv.h"
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#include "v3d_regs.h"
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#define V3D_MMU_PAGE_SHIFT 12
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/* Note: All PTEs for the 1MB superpage must be filled with the
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* superpage bit set.
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*/
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#define V3D_PTE_SUPERPAGE BIT(31)
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#define V3D_PTE_WRITEABLE BIT(29)
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#define V3D_PTE_VALID BIT(28)
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static int v3d_mmu_flush_all(struct v3d_dev *v3d)
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{
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int ret;
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/* Make sure that another flush isn't already running when we
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* start this one.
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*/
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ret = wait_for(!(V3D_READ(V3D_MMU_CTL) &
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V3D_MMU_CTL_TLB_CLEARING), 100);
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if (ret)
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dev_err(v3d->drm.dev, "TLB clear wait idle pre-wait failed\n");
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V3D_WRITE(V3D_MMU_CTL, V3D_READ(V3D_MMU_CTL) |
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V3D_MMU_CTL_TLB_CLEAR);
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V3D_WRITE(V3D_MMUC_CONTROL,
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V3D_MMUC_CONTROL_FLUSH |
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V3D_MMUC_CONTROL_ENABLE);
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ret = wait_for(!(V3D_READ(V3D_MMU_CTL) &
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V3D_MMU_CTL_TLB_CLEARING), 100);
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if (ret) {
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dev_err(v3d->drm.dev, "TLB clear wait idle failed\n");
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return ret;
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}
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ret = wait_for(!(V3D_READ(V3D_MMUC_CONTROL) &
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V3D_MMUC_CONTROL_FLUSHING), 100);
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if (ret)
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dev_err(v3d->drm.dev, "MMUC flush wait idle failed\n");
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return ret;
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}
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int v3d_mmu_set_page_table(struct v3d_dev *v3d)
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{
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V3D_WRITE(V3D_MMU_PT_PA_BASE, v3d->pt_paddr >> V3D_MMU_PAGE_SHIFT);
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V3D_WRITE(V3D_MMU_CTL,
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V3D_MMU_CTL_ENABLE |
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V3D_MMU_CTL_PT_INVALID_ENABLE |
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V3D_MMU_CTL_PT_INVALID_ABORT |
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V3D_MMU_CTL_PT_INVALID_INT |
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V3D_MMU_CTL_WRITE_VIOLATION_ABORT |
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V3D_MMU_CTL_WRITE_VIOLATION_INT |
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V3D_MMU_CTL_CAP_EXCEEDED_ABORT |
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V3D_MMU_CTL_CAP_EXCEEDED_INT);
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V3D_WRITE(V3D_MMU_ILLEGAL_ADDR,
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(v3d->mmu_scratch_paddr >> V3D_MMU_PAGE_SHIFT) |
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V3D_MMU_ILLEGAL_ADDR_ENABLE);
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V3D_WRITE(V3D_MMUC_CONTROL, V3D_MMUC_CONTROL_ENABLE);
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return v3d_mmu_flush_all(v3d);
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}
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void v3d_mmu_insert_ptes(struct v3d_bo *bo)
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{
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struct drm_gem_shmem_object *shmem_obj = &bo->base;
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struct v3d_dev *v3d = to_v3d_dev(shmem_obj->base.dev);
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u32 page = bo->node.start;
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u32 page_prot = V3D_PTE_WRITEABLE | V3D_PTE_VALID;
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struct sg_dma_page_iter dma_iter;
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for_each_sgtable_dma_page(shmem_obj->sgt, &dma_iter, 0) {
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dma_addr_t dma_addr = sg_page_iter_dma_address(&dma_iter);
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u32 page_address = dma_addr >> V3D_MMU_PAGE_SHIFT;
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u32 pte = page_prot | page_address;
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u32 i;
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BUG_ON(page_address + (PAGE_SIZE >> V3D_MMU_PAGE_SHIFT) >=
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BIT(24));
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for (i = 0; i < PAGE_SIZE >> V3D_MMU_PAGE_SHIFT; i++)
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v3d->pt[page++] = pte + i;
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}
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WARN_ON_ONCE(page - bo->node.start !=
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shmem_obj->base.size >> V3D_MMU_PAGE_SHIFT);
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if (v3d_mmu_flush_all(v3d))
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dev_err(v3d->drm.dev, "MMU flush timeout\n");
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}
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void v3d_mmu_remove_ptes(struct v3d_bo *bo)
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{
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struct v3d_dev *v3d = to_v3d_dev(bo->base.base.dev);
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u32 npages = bo->base.base.size >> V3D_MMU_PAGE_SHIFT;
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u32 page;
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for (page = bo->node.start; page < bo->node.start + npages; page++)
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v3d->pt[page] = 0;
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if (v3d_mmu_flush_all(v3d))
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dev_err(v3d->drm.dev, "MMU flush timeout\n");
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}
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