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001a30c4d0
On ARMv5 and above, it is beneficial to use compiler built-ins such as __builtin_ffs() and __builtin_ctzl() to implement ffs(), __ffs(), fls() and __fls(). The compiler does inline the clz instruction and even the rbit instruction when available, or provide a constant value when possible. On ARMv4 the compiler calls out to helper functions for those built-ins so it is best to keep the open coded versions in that case. Signed-off-by: Nicolas Pitre <nico@linaro.org> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
278 lines
7.4 KiB
C
278 lines
7.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright 1995, Russell King.
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* Various bits and pieces copyrights include:
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* Linus Torvalds (test_bit).
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* Big endian support: Copyright 2001, Nicolas Pitre
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* reworked by rmk.
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*
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* bit 0 is the LSB of an "unsigned long" quantity.
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*
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* Please note that the code in this file should never be included
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* from user space. Many of these are not implemented in assembler
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* since they would be too costly. Also, they require privileged
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* instructions (which are not available from user mode) to ensure
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* that they are atomic.
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*/
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#ifndef __ASM_ARM_BITOPS_H
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#define __ASM_ARM_BITOPS_H
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#ifdef __KERNEL__
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#ifndef _LINUX_BITOPS_H
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#error only <linux/bitops.h> can be included directly
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#endif
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#include <linux/compiler.h>
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#include <linux/irqflags.h>
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#include <asm/barrier.h>
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/*
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* These functions are the basis of our bit ops.
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*
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* First, the atomic bitops. These use native endian.
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*/
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static inline void ____atomic_set_bit(unsigned int bit, volatile unsigned long *p)
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{
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unsigned long flags;
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unsigned long mask = BIT_MASK(bit);
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p += BIT_WORD(bit);
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raw_local_irq_save(flags);
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*p |= mask;
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raw_local_irq_restore(flags);
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}
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static inline void ____atomic_clear_bit(unsigned int bit, volatile unsigned long *p)
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{
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unsigned long flags;
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unsigned long mask = BIT_MASK(bit);
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p += BIT_WORD(bit);
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raw_local_irq_save(flags);
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*p &= ~mask;
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raw_local_irq_restore(flags);
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}
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static inline void ____atomic_change_bit(unsigned int bit, volatile unsigned long *p)
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{
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unsigned long flags;
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unsigned long mask = BIT_MASK(bit);
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p += BIT_WORD(bit);
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raw_local_irq_save(flags);
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*p ^= mask;
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raw_local_irq_restore(flags);
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}
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static inline int
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____atomic_test_and_set_bit(unsigned int bit, volatile unsigned long *p)
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{
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unsigned long flags;
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unsigned int res;
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unsigned long mask = BIT_MASK(bit);
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p += BIT_WORD(bit);
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raw_local_irq_save(flags);
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res = *p;
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*p = res | mask;
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raw_local_irq_restore(flags);
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return (res & mask) != 0;
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}
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static inline int
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____atomic_test_and_clear_bit(unsigned int bit, volatile unsigned long *p)
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{
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unsigned long flags;
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unsigned int res;
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unsigned long mask = BIT_MASK(bit);
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p += BIT_WORD(bit);
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raw_local_irq_save(flags);
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res = *p;
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*p = res & ~mask;
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raw_local_irq_restore(flags);
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return (res & mask) != 0;
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}
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static inline int
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____atomic_test_and_change_bit(unsigned int bit, volatile unsigned long *p)
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{
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unsigned long flags;
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unsigned int res;
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unsigned long mask = BIT_MASK(bit);
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p += BIT_WORD(bit);
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raw_local_irq_save(flags);
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res = *p;
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*p = res ^ mask;
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raw_local_irq_restore(flags);
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return (res & mask) != 0;
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}
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#include <asm-generic/bitops/non-atomic.h>
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/*
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* A note about Endian-ness.
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* -------------------------
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*
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* When the ARM is put into big endian mode via CR15, the processor
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* merely swaps the order of bytes within words, thus:
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*
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* ------------ physical data bus bits -----------
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* D31 ... D24 D23 ... D16 D15 ... D8 D7 ... D0
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* little byte 3 byte 2 byte 1 byte 0
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* big byte 0 byte 1 byte 2 byte 3
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*
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* This means that reading a 32-bit word at address 0 returns the same
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* value irrespective of the endian mode bit.
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*
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* Peripheral devices should be connected with the data bus reversed in
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* "Big Endian" mode. ARM Application Note 61 is applicable, and is
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* available from http://www.arm.com/.
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*
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* The following assumes that the data bus connectivity for big endian
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* mode has been followed.
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*
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* Note that bit 0 is defined to be 32-bit word bit 0, not byte 0 bit 0.
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*/
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/*
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* Native endian assembly bitops. nr = 0 -> word 0 bit 0.
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*/
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extern void _set_bit(int nr, volatile unsigned long * p);
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extern void _clear_bit(int nr, volatile unsigned long * p);
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extern void _change_bit(int nr, volatile unsigned long * p);
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extern int _test_and_set_bit(int nr, volatile unsigned long * p);
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extern int _test_and_clear_bit(int nr, volatile unsigned long * p);
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extern int _test_and_change_bit(int nr, volatile unsigned long * p);
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/*
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* Little endian assembly bitops. nr = 0 -> byte 0 bit 0.
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*/
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extern int _find_first_zero_bit_le(const unsigned long *p, unsigned size);
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extern int _find_next_zero_bit_le(const unsigned long *p, int size, int offset);
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extern int _find_first_bit_le(const unsigned long *p, unsigned size);
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extern int _find_next_bit_le(const unsigned long *p, int size, int offset);
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/*
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* Big endian assembly bitops. nr = 0 -> byte 3 bit 0.
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*/
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extern int _find_first_zero_bit_be(const unsigned long *p, unsigned size);
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extern int _find_next_zero_bit_be(const unsigned long *p, int size, int offset);
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extern int _find_first_bit_be(const unsigned long *p, unsigned size);
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extern int _find_next_bit_be(const unsigned long *p, int size, int offset);
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#ifndef CONFIG_SMP
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/*
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* The __* form of bitops are non-atomic and may be reordered.
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*/
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#define ATOMIC_BITOP(name,nr,p) \
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(__builtin_constant_p(nr) ? ____atomic_##name(nr, p) : _##name(nr,p))
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#else
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#define ATOMIC_BITOP(name,nr,p) _##name(nr,p)
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#endif
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/*
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* Native endian atomic definitions.
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*/
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#define set_bit(nr,p) ATOMIC_BITOP(set_bit,nr,p)
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#define clear_bit(nr,p) ATOMIC_BITOP(clear_bit,nr,p)
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#define change_bit(nr,p) ATOMIC_BITOP(change_bit,nr,p)
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#define test_and_set_bit(nr,p) ATOMIC_BITOP(test_and_set_bit,nr,p)
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#define test_and_clear_bit(nr,p) ATOMIC_BITOP(test_and_clear_bit,nr,p)
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#define test_and_change_bit(nr,p) ATOMIC_BITOP(test_and_change_bit,nr,p)
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#ifndef __ARMEB__
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/*
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* These are the little endian, atomic definitions.
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*/
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#define find_first_zero_bit(p,sz) _find_first_zero_bit_le(p,sz)
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#define find_next_zero_bit(p,sz,off) _find_next_zero_bit_le(p,sz,off)
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#define find_first_bit(p,sz) _find_first_bit_le(p,sz)
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#define find_next_bit(p,sz,off) _find_next_bit_le(p,sz,off)
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#else
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/*
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* These are the big endian, atomic definitions.
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*/
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#define find_first_zero_bit(p,sz) _find_first_zero_bit_be(p,sz)
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#define find_next_zero_bit(p,sz,off) _find_next_zero_bit_be(p,sz,off)
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#define find_first_bit(p,sz) _find_first_bit_be(p,sz)
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#define find_next_bit(p,sz,off) _find_next_bit_be(p,sz,off)
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#endif
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#if __LINUX_ARM_ARCH__ < 5
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#include <asm-generic/bitops/__fls.h>
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#include <asm-generic/bitops/__ffs.h>
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#include <asm-generic/bitops/fls.h>
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#include <asm-generic/bitops/ffs.h>
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#else
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/*
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* On ARMv5 and above, the gcc built-ins may rely on the clz instruction
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* and produce optimal inlined code in all cases. On ARMv7 it is even
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* better by also using the rbit instruction.
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*/
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#include <asm-generic/bitops/builtin-__fls.h>
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#include <asm-generic/bitops/builtin-__ffs.h>
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#include <asm-generic/bitops/builtin-fls.h>
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#include <asm-generic/bitops/builtin-ffs.h>
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#endif
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#include <asm-generic/bitops/ffz.h>
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#include <asm-generic/bitops/fls64.h>
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#include <asm-generic/bitops/sched.h>
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#include <asm-generic/bitops/hweight.h>
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#include <asm-generic/bitops/lock.h>
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#ifdef __ARMEB__
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static inline int find_first_zero_bit_le(const void *p, unsigned size)
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{
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return _find_first_zero_bit_le(p, size);
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}
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#define find_first_zero_bit_le find_first_zero_bit_le
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static inline int find_next_zero_bit_le(const void *p, int size, int offset)
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{
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return _find_next_zero_bit_le(p, size, offset);
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}
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#define find_next_zero_bit_le find_next_zero_bit_le
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static inline int find_next_bit_le(const void *p, int size, int offset)
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{
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return _find_next_bit_le(p, size, offset);
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}
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#define find_next_bit_le find_next_bit_le
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#endif
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#include <asm-generic/bitops/find.h>
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#include <asm-generic/bitops/le.h>
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/*
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* Ext2 is defined to use little-endian byte ordering.
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*/
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#include <asm-generic/bitops/ext2-atomic-setbit.h>
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#endif /* __KERNEL__ */
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#endif /* _ARM_BITOPS_H */
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