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e9ae440c97
Split out the common SPMI PMIC arbiter properties for QCOM devices into a separate file so that it can be included as a reference for devices using them. This will be needed for the upcoming PMIC v8 arbiter support patch, as the v8 arbiter also uses these common properties. Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Jishnu Prakash <jishnu.prakash@oss.qualcomm.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org> Link: https://patch.msgid.link/20260123182039.224314-8-sboyd@kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
114 lines
2.8 KiB
YAML
114 lines
2.8 KiB
YAML
# SPDX-License-Identifier: GPL-2.0-only
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/spmi/qcom,spmi-pmic-arb.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm SPMI Controller (PMIC Arbiter)
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maintainers:
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- Stephen Boyd <sboyd@kernel.org>
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description: |
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The SPMI PMIC Arbiter is found on Snapdragon chipsets. It is an SPMI
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controller with wrapping arbitration logic to allow for multiple on-chip
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devices to control a single SPMI master.
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The PMIC Arbiter can also act as an interrupt controller, providing interrupts
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to slave devices.
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allOf:
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- $ref: spmi.yaml
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- $ref: qcom,spmi-pmic-arb-common.yaml
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properties:
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compatible:
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const: qcom,spmi-pmic-arb
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reg:
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oneOf:
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- items: # V1
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- description: core registers
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- description: interrupt controller registers
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- description: configuration registers
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- items: # V2
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- description: core registers
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- description: tx-channel per virtual slave regosters
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- description: rx-channel (called observer) per virtual slave registers
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- description: interrupt controller registers
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- description: configuration registers
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reg-names:
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oneOf:
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- items:
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- const: core
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- const: intr
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- const: cnfg
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- items:
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- const: core
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- const: chnls
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- const: obsrvr
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- const: intr
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- const: cnfg
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interrupts:
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maxItems: 1
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interrupt-names:
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const: periph_irq
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interrupt-controller: true
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'#address-cells': true
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'#interrupt-cells':
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const: 4
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description: |
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cell 1: slave ID for the requested interrupt (0-15)
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cell 2: peripheral ID for requested interrupt (0-255)
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cell 3: the requested peripheral interrupt (0-7)
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cell 4: interrupt flags indicating level-sense information,
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as defined in dt-bindings/interrupt-controller/irq.h
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'#size-cells': true
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qcom,bus-id:
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$ref: /schemas/types.yaml#/definitions/uint32
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minimum: 0
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maximum: 1
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description: >
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SPMI bus instance. only applicable to PMIC arbiter version 7 and beyond.
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Supported values, 0 = primary bus, 1 = secondary bus
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deprecated: true
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required:
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- compatible
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- reg-names
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unevaluatedProperties: false
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examples:
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- |
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spmi@fc4cf000 {
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compatible = "qcom,spmi-pmic-arb";
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reg-names = "core", "intr", "cnfg";
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reg = <0xfc4cf000 0x1000>,
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<0xfc4cb000 0x1000>,
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<0xfc4ca000 0x1000>;
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interrupt-names = "periph_irq";
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interrupts = <0 190 0>;
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qcom,ee = <0>;
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qcom,channel = <0>;
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#address-cells = <2>;
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#size-cells = <0>;
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interrupt-controller;
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#interrupt-cells = <4>;
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qcom,bus-id = <0>;
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};
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