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cbb382c5fb
Add driver for the Qualcomm interconnect buses found in SDX55 based platforms. The topology consists of several NoCs that are controlled by a remote processor that collects the aggregated bandwidth for each master-slave pairs. Based on SM8250 driver and generated from downstream dts. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20210121053254.8355-3-manivannan.sadhasivam@linaro.org Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
71 lines
2.1 KiB
C
71 lines
2.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2021, Linaro Ltd.
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*/
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#ifndef __DRIVERS_INTERCONNECT_QCOM_SDX55_H
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#define __DRIVERS_INTERCONNECT_QCOM_SDX55_H
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#define SDX55_MASTER_IPA_CORE 0
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#define SDX55_MASTER_LLCC 1
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#define SDX55_MASTER_TCU_0 2
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#define SDX55_MASTER_SNOC_GC_MEM_NOC 3
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#define SDX55_MASTER_AMPSS_M0 4
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#define SDX55_MASTER_AUDIO 5
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#define SDX55_MASTER_BLSP_1 6
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#define SDX55_MASTER_QDSS_BAM 7
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#define SDX55_MASTER_QPIC 8
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#define SDX55_MASTER_SNOC_CFG 9
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#define SDX55_MASTER_SPMI_FETCHER 10
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#define SDX55_MASTER_ANOC_SNOC 11
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#define SDX55_MASTER_IPA 12
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#define SDX55_MASTER_MEM_NOC_SNOC 13
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#define SDX55_MASTER_MEM_NOC_PCIE_SNOC 14
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#define SDX55_MASTER_CRYPTO_CORE_0 15
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#define SDX55_MASTER_EMAC 16
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#define SDX55_MASTER_IPA_PCIE 17
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#define SDX55_MASTER_PCIE 18
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#define SDX55_MASTER_QDSS_ETR 19
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#define SDX55_MASTER_SDCC_1 20
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#define SDX55_MASTER_USB3 21
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#define SDX55_SLAVE_IPA_CORE 22
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#define SDX55_SLAVE_EBI_CH0 23
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#define SDX55_SLAVE_LLCC 24
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#define SDX55_SLAVE_MEM_NOC_SNOC 25
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#define SDX55_SLAVE_MEM_NOC_PCIE_SNOC 26
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#define SDX55_SLAVE_ANOC_SNOC 27
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#define SDX55_SLAVE_SNOC_CFG 28
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#define SDX55_SLAVE_EMAC_CFG 29
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#define SDX55_SLAVE_USB3 30
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#define SDX55_SLAVE_TLMM 31
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#define SDX55_SLAVE_SPMI_FETCHER 32
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#define SDX55_SLAVE_QDSS_CFG 33
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#define SDX55_SLAVE_PDM 34
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#define SDX55_SLAVE_SNOC_MEM_NOC_GC 35
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#define SDX55_SLAVE_TCSR 36
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#define SDX55_SLAVE_CNOC_DDRSS 37
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#define SDX55_SLAVE_SPMI_VGI_COEX 38
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#define SDX55_SLAVE_QPIC 39
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#define SDX55_SLAVE_OCIMEM 40
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#define SDX55_SLAVE_IPA_CFG 41
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#define SDX55_SLAVE_USB3_PHY_CFG 42
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#define SDX55_SLAVE_AOP 43
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#define SDX55_SLAVE_BLSP_1 44
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#define SDX55_SLAVE_SDCC_1 45
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#define SDX55_SLAVE_CNOC_MSS 46
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#define SDX55_SLAVE_PCIE_PARF 47
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#define SDX55_SLAVE_ECC_CFG 48
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#define SDX55_SLAVE_AUDIO 49
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#define SDX55_SLAVE_AOSS 51
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#define SDX55_SLAVE_PRNG 52
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#define SDX55_SLAVE_CRYPTO_0_CFG 53
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#define SDX55_SLAVE_TCU 54
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#define SDX55_SLAVE_CLK_CTL 55
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#define SDX55_SLAVE_IMEM_CFG 56
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#define SDX55_SLAVE_SERVICE_SNOC 57
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#define SDX55_SLAVE_PCIE_0 58
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#define SDX55_SLAVE_QDSS_STM 59
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#define SDX55_SLAVE_APPSS 60
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#endif
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