Dmytro Laktyushkin 62f0576c42 drm/amd/display: fix dcn315 memory channel count and width read ... [Why & How] Correctly set ddr5 channel width to 8 bytes Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Wayne Lin <wayne.lin@amd.com> Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2022-09-19 15:09:44 -04:00
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dcn31_fpu.c	drm/amd/display: fix dcn315 memory channel count and width read	2022-09-19 15:09:44 -04:00
dcn31_fpu.h	drm/amd/display: fix soft-fp vs hard-fp on DCN 3.1 family for powerpc	2022-07-25 09:31:05 -04:00
display_mode_vba_31.c	drm/amd/display: clean up some inconsistent indentings	2022-09-19 15:07:51 -04:00
display_mode_vba_31.h
display_rq_dlg_calc_31.c	drm/amd/display: Modify header inclusion pattern	2022-08-16 18:08:42 -04:00
display_rq_dlg_calc_31.h	drm/amd/display: Pass display_pipe_params_st as const in DML	2021-09-23 15:17:29 -04:00