Peterson eda7f2e9bb drm/amd/display: Fix low black values by increasing error ... [WHY] Regamma resolution for the first few black levels can have problems for calibration. [HOW] HW LUT is divided into N power-of-2 regions each with K segments. For SDR mode we set min point at 2^-10 and increments of 2^-13. It's generally more than 8-bit SDR needs, but some calibration tools and API use 12-bit curves. The fix shifts starting point to 2^-12 and starting increments at 2^-16. Reviewed-by: Krunoslav Kovac <krunoslav.kovac@amd.com> Signed-off-by: Peterson <peterson.guo@amd.com> Signed-off-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2024-10-07 14:12:01 -04:00
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dcn30_afmt.c	drm/amd/display: Remove unused local variables	2023-02-23 17:36:00 -05:00
dcn30_afmt.h	drm/amd/display: Add VPG and AFMT low power support for DCN3.1	2021-09-14 15:57:11 -04:00
dcn30_cm_common.c	drm/amd/display: Fix low black values by increasing error	2024-10-07 14:12:01 -04:00
dcn30_mmhubbub.c	drm/amd/display: change several dcn30 variables storage-class-specifier to static	2023-03-07 14:22:42 -05:00
dcn30_mmhubbub.h	drm/amd/display: rework macros for DWB register access	2022-11-15 13:35:15 -05:00
dcn30_opp.h	drm/amd/display: Add DCN3 OPP header	2020-07-01 01:59:14 -04:00
dcn30_vpg.c	drm/amd/display: Fix issue with dynamic bpp change for DCN3x	2021-09-23 15:17:30 -04:00
dcn30_vpg.h	drm/amd/display: refactor vpg.h	2024-04-09 22:16:02 -04:00
Makefile	drm/amd/display: Refactoring HPO	2024-07-23 17:35:45 -04:00