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e216ce60a9
The APQ8064 multimedia clock controller is fairly similar to the 8960 multimedia clock controller, except that gfx2d0/1 has been removed and the gfx3d frequency is slightly faster when using the newly introduced PLL15. We also add vcap clocks and a couple new TV clocks. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
102 lines
3.0 KiB
C
102 lines
3.0 KiB
C
/*
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* Copyright (c) 2013, The Linux Foundation. All rights reserved.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _DT_BINDINGS_RESET_MSM_MMCC_8960_H
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#define _DT_BINDINGS_RESET_MSM_MMCC_8960_H
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#define VPE_AXI_RESET 0
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#define IJPEG_AXI_RESET 1
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#define MPD_AXI_RESET 2
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#define VFE_AXI_RESET 3
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#define SP_AXI_RESET 4
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#define VCODEC_AXI_RESET 5
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#define ROT_AXI_RESET 6
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#define VCODEC_AXI_A_RESET 7
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#define VCODEC_AXI_B_RESET 8
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#define FAB_S3_AXI_RESET 9
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#define FAB_S2_AXI_RESET 10
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#define FAB_S1_AXI_RESET 11
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#define FAB_S0_AXI_RESET 12
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#define SMMU_GFX3D_ABH_RESET 13
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#define SMMU_VPE_AHB_RESET 14
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#define SMMU_VFE_AHB_RESET 15
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#define SMMU_ROT_AHB_RESET 16
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#define SMMU_VCODEC_B_AHB_RESET 17
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#define SMMU_VCODEC_A_AHB_RESET 18
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#define SMMU_MDP1_AHB_RESET 19
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#define SMMU_MDP0_AHB_RESET 20
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#define SMMU_JPEGD_AHB_RESET 21
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#define SMMU_IJPEG_AHB_RESET 22
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#define SMMU_GFX2D0_AHB_RESET 23
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#define SMMU_GFX2D1_AHB_RESET 24
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#define APU_AHB_RESET 25
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#define CSI_AHB_RESET 26
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#define TV_ENC_AHB_RESET 27
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#define VPE_AHB_RESET 28
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#define FABRIC_AHB_RESET 29
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#define GFX2D0_AHB_RESET 30
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#define GFX2D1_AHB_RESET 31
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#define GFX3D_AHB_RESET 32
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#define HDMI_AHB_RESET 33
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#define MSSS_IMEM_AHB_RESET 34
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#define IJPEG_AHB_RESET 35
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#define DSI_M_AHB_RESET 36
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#define DSI_S_AHB_RESET 37
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#define JPEGD_AHB_RESET 38
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#define MDP_AHB_RESET 39
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#define ROT_AHB_RESET 40
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#define VCODEC_AHB_RESET 41
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#define VFE_AHB_RESET 42
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#define DSI2_M_AHB_RESET 43
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#define DSI2_S_AHB_RESET 44
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#define CSIPHY2_RESET 45
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#define CSI_PIX1_RESET 46
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#define CSIPHY0_RESET 47
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#define CSIPHY1_RESET 48
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#define DSI2_RESET 49
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#define VFE_CSI_RESET 50
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#define MDP_RESET 51
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#define AMP_RESET 52
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#define JPEGD_RESET 53
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#define CSI1_RESET 54
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#define VPE_RESET 55
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#define MMSS_FABRIC_RESET 56
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#define VFE_RESET 57
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#define GFX2D0_RESET 58
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#define GFX2D1_RESET 59
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#define GFX3D_RESET 60
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#define HDMI_RESET 61
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#define MMSS_IMEM_RESET 62
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#define IJPEG_RESET 63
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#define CSI0_RESET 64
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#define DSI_RESET 65
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#define VCODEC_RESET 66
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#define MDP_TV_RESET 67
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#define MDP_VSYNC_RESET 68
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#define ROT_RESET 69
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#define TV_HDMI_RESET 70
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#define TV_ENC_RESET 71
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#define CSI2_RESET 72
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#define CSI_RDI1_RESET 73
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#define CSI_RDI2_RESET 74
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#define GFX3D_AXI_RESET 75
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#define VCAP_AXI_RESET 76
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#define SMMU_VCAP_AHB_RESET 77
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#define VCAP_AHB_RESET 78
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#define CSI_RDI_RESET 79
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#define CSI_PIX_RESET 80
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#define VCAP_NPL_RESET 81
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#define VCAP_RESET 82
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#endif
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