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The AXM55xx family consists of devices that may contain up to 16 ARM Cortex-A15 cores (in a 4x4 cluster configuration). The cores within each cluster share an L2 cache, and the clusters are connected to each other via a CCN-504 cache coherent interconnect. This machine requires CONFIG_ARM_LPAE enabled as all peripherals are located above 4GB in the memory map. Signed-off-by: Anders Berg <anders.berg@lsi.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
29 lines
861 B
C
29 lines
861 B
C
/*
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* Support for the LSI Axxia SoC devices based on ARM cores.
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*
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* Copyright (C) 2012 LSI
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/init.h>
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#include <asm/mach/arch.h>
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static const char *axxia_dt_match[] __initconst = {
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"lsi,axm5516",
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"lsi,axm5516-sim",
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"lsi,axm5516-emu",
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NULL
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};
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DT_MACHINE_START(AXXIA_DT, "LSI Axxia AXM55XX")
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.dt_compat = axxia_dt_match,
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MACHINE_END
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