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git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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8e958839e4
The "SRMMU" supports 4k pages using a fixed three-level walk with a
256-entry PGD and 64-entry PMD/PTE levels. In order to fill a page
with a 'pgtable_t', the SRMMU code allocates four native PTE tables
into a single PTE allocation and similarly for the PMD level, leading
to an array of 16 physical pointers in a 'pmd_t'
This breaks the generic code which assumes READ_ONCE(*pmd) will be
word sized.
In a manner similar to ef22d8abd8 ("m68k: mm: Restructure Motorola
MMU page-table layout"), this patch implements the native page-table
setup directly. This significantly increases the page-table memory
overhead, but will be addresses in a subsequent patch.
Cc: "David S. Miller" <davem@davemloft.net>
Cc: Peter Zijlstra <peterz@infradead.org>
Signed-off-by: Will Deacon <will@kernel.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
415 lines
9.5 KiB
ArmAsm
415 lines
9.5 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* hypersparc.S: High speed Hypersparc mmu/cache operations.
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*
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* Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
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*/
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#include <asm/ptrace.h>
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#include <asm/psr.h>
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#include <asm/asm-offsets.h>
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#include <asm/asi.h>
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#include <asm/page.h>
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#include <asm/pgtable.h>
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#include <asm/pgtsrmmu.h>
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#include <linux/init.h>
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.text
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.align 4
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.globl hypersparc_flush_cache_all, hypersparc_flush_cache_mm
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.globl hypersparc_flush_cache_range, hypersparc_flush_cache_page
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.globl hypersparc_flush_page_to_ram
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.globl hypersparc_flush_page_for_dma, hypersparc_flush_sig_insns
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.globl hypersparc_flush_tlb_all, hypersparc_flush_tlb_mm
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.globl hypersparc_flush_tlb_range, hypersparc_flush_tlb_page
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hypersparc_flush_cache_all:
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WINDOW_FLUSH(%g4, %g5)
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sethi %hi(vac_cache_size), %g4
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ld [%g4 + %lo(vac_cache_size)], %g5
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sethi %hi(vac_line_size), %g1
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ld [%g1 + %lo(vac_line_size)], %g2
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1:
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subcc %g5, %g2, %g5 ! hyper_flush_unconditional_combined
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bne 1b
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sta %g0, [%g5] ASI_M_FLUSH_CTX
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retl
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sta %g0, [%g0] ASI_M_FLUSH_IWHOLE ! hyper_flush_whole_icache
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/* We expand the window flush to get maximum performance. */
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hypersparc_flush_cache_mm:
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#ifndef CONFIG_SMP
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ld [%o0 + AOFF_mm_context], %g1
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cmp %g1, -1
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be hypersparc_flush_cache_mm_out
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#endif
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WINDOW_FLUSH(%g4, %g5)
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sethi %hi(vac_line_size), %g1
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ld [%g1 + %lo(vac_line_size)], %o1
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sethi %hi(vac_cache_size), %g2
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ld [%g2 + %lo(vac_cache_size)], %o0
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add %o1, %o1, %g1
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add %o1, %g1, %g2
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add %o1, %g2, %g3
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add %o1, %g3, %g4
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add %o1, %g4, %g5
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add %o1, %g5, %o4
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add %o1, %o4, %o5
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/* BLAMMO! */
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1:
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subcc %o0, %o5, %o0 ! hyper_flush_cache_user
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sta %g0, [%o0 + %g0] ASI_M_FLUSH_USER
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sta %g0, [%o0 + %o1] ASI_M_FLUSH_USER
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sta %g0, [%o0 + %g1] ASI_M_FLUSH_USER
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sta %g0, [%o0 + %g2] ASI_M_FLUSH_USER
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sta %g0, [%o0 + %g3] ASI_M_FLUSH_USER
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sta %g0, [%o0 + %g4] ASI_M_FLUSH_USER
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sta %g0, [%o0 + %g5] ASI_M_FLUSH_USER
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bne 1b
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sta %g0, [%o0 + %o4] ASI_M_FLUSH_USER
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hypersparc_flush_cache_mm_out:
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retl
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nop
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/* The things we do for performance... */
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hypersparc_flush_cache_range:
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ld [%o0 + VMA_VM_MM], %o0
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#ifndef CONFIG_SMP
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ld [%o0 + AOFF_mm_context], %g1
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cmp %g1, -1
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be hypersparc_flush_cache_range_out
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#endif
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WINDOW_FLUSH(%g4, %g5)
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sethi %hi(vac_line_size), %g1
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ld [%g1 + %lo(vac_line_size)], %o4
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sethi %hi(vac_cache_size), %g2
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ld [%g2 + %lo(vac_cache_size)], %o3
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/* Here comes the fun part... */
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add %o2, (PAGE_SIZE - 1), %o2
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andn %o1, (PAGE_SIZE - 1), %o1
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add %o4, %o4, %o5
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andn %o2, (PAGE_SIZE - 1), %o2
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add %o4, %o5, %g1
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sub %o2, %o1, %g4
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add %o4, %g1, %g2
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sll %o3, 2, %g5
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add %o4, %g2, %g3
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cmp %g4, %g5
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add %o4, %g3, %g4
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blu 0f
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add %o4, %g4, %g5
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add %o4, %g5, %g7
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/* Flush entire user space, believe it or not this is quicker
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* than page at a time flushings for range > (cache_size<<2).
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*/
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1:
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subcc %o3, %g7, %o3
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sta %g0, [%o3 + %g0] ASI_M_FLUSH_USER
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sta %g0, [%o3 + %o4] ASI_M_FLUSH_USER
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sta %g0, [%o3 + %o5] ASI_M_FLUSH_USER
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sta %g0, [%o3 + %g1] ASI_M_FLUSH_USER
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sta %g0, [%o3 + %g2] ASI_M_FLUSH_USER
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sta %g0, [%o3 + %g3] ASI_M_FLUSH_USER
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sta %g0, [%o3 + %g4] ASI_M_FLUSH_USER
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bne 1b
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sta %g0, [%o3 + %g5] ASI_M_FLUSH_USER
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retl
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nop
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/* Below our threshold, flush one page at a time. */
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0:
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ld [%o0 + AOFF_mm_context], %o0
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mov SRMMU_CTX_REG, %g7
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lda [%g7] ASI_M_MMUREGS, %o3
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sta %o0, [%g7] ASI_M_MMUREGS
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add %o2, -PAGE_SIZE, %o0
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1:
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or %o0, 0x400, %g7
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lda [%g7] ASI_M_FLUSH_PROBE, %g7
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orcc %g7, 0, %g0
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be,a 3f
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mov %o0, %o2
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add %o4, %g5, %g7
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2:
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sub %o2, %g7, %o2
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sta %g0, [%o2 + %g0] ASI_M_FLUSH_PAGE
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sta %g0, [%o2 + %o4] ASI_M_FLUSH_PAGE
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sta %g0, [%o2 + %o5] ASI_M_FLUSH_PAGE
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sta %g0, [%o2 + %g1] ASI_M_FLUSH_PAGE
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sta %g0, [%o2 + %g2] ASI_M_FLUSH_PAGE
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sta %g0, [%o2 + %g3] ASI_M_FLUSH_PAGE
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andcc %o2, 0xffc, %g0
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sta %g0, [%o2 + %g4] ASI_M_FLUSH_PAGE
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bne 2b
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sta %g0, [%o2 + %g5] ASI_M_FLUSH_PAGE
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3:
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cmp %o2, %o1
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bne 1b
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add %o2, -PAGE_SIZE, %o0
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mov SRMMU_FAULT_STATUS, %g5
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lda [%g5] ASI_M_MMUREGS, %g0
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mov SRMMU_CTX_REG, %g7
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sta %o3, [%g7] ASI_M_MMUREGS
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hypersparc_flush_cache_range_out:
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retl
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nop
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/* HyperSparc requires a valid mapping where we are about to flush
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* in order to check for a physical tag match during the flush.
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*/
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/* Verified, my ass... */
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hypersparc_flush_cache_page:
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ld [%o0 + VMA_VM_MM], %o0
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ld [%o0 + AOFF_mm_context], %g2
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#ifndef CONFIG_SMP
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cmp %g2, -1
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be hypersparc_flush_cache_page_out
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#endif
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WINDOW_FLUSH(%g4, %g5)
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sethi %hi(vac_line_size), %g1
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ld [%g1 + %lo(vac_line_size)], %o4
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mov SRMMU_CTX_REG, %o3
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andn %o1, (PAGE_SIZE - 1), %o1
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lda [%o3] ASI_M_MMUREGS, %o2
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sta %g2, [%o3] ASI_M_MMUREGS
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or %o1, 0x400, %o5
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lda [%o5] ASI_M_FLUSH_PROBE, %g1
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orcc %g0, %g1, %g0
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be 2f
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add %o4, %o4, %o5
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sub %o1, -PAGE_SIZE, %o1
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add %o4, %o5, %g1
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add %o4, %g1, %g2
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add %o4, %g2, %g3
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add %o4, %g3, %g4
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add %o4, %g4, %g5
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add %o4, %g5, %g7
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/* BLAMMO! */
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1:
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sub %o1, %g7, %o1
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sta %g0, [%o1 + %g0] ASI_M_FLUSH_PAGE
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sta %g0, [%o1 + %o4] ASI_M_FLUSH_PAGE
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sta %g0, [%o1 + %o5] ASI_M_FLUSH_PAGE
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sta %g0, [%o1 + %g1] ASI_M_FLUSH_PAGE
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sta %g0, [%o1 + %g2] ASI_M_FLUSH_PAGE
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sta %g0, [%o1 + %g3] ASI_M_FLUSH_PAGE
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andcc %o1, 0xffc, %g0
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sta %g0, [%o1 + %g4] ASI_M_FLUSH_PAGE
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bne 1b
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sta %g0, [%o1 + %g5] ASI_M_FLUSH_PAGE
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2:
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mov SRMMU_FAULT_STATUS, %g7
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mov SRMMU_CTX_REG, %g4
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lda [%g7] ASI_M_MMUREGS, %g0
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sta %o2, [%g4] ASI_M_MMUREGS
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hypersparc_flush_cache_page_out:
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retl
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nop
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hypersparc_flush_sig_insns:
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flush %o1
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retl
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flush %o1 + 4
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/* HyperSparc is copy-back. */
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hypersparc_flush_page_to_ram:
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sethi %hi(vac_line_size), %g1
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ld [%g1 + %lo(vac_line_size)], %o4
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andn %o0, (PAGE_SIZE - 1), %o0
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add %o4, %o4, %o5
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or %o0, 0x400, %g7
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lda [%g7] ASI_M_FLUSH_PROBE, %g5
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add %o4, %o5, %g1
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orcc %g5, 0, %g0
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be 2f
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add %o4, %g1, %g2
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add %o4, %g2, %g3
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sub %o0, -PAGE_SIZE, %o0
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add %o4, %g3, %g4
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add %o4, %g4, %g5
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add %o4, %g5, %g7
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/* BLAMMO! */
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1:
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sub %o0, %g7, %o0
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sta %g0, [%o0 + %g0] ASI_M_FLUSH_PAGE
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sta %g0, [%o0 + %o4] ASI_M_FLUSH_PAGE
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sta %g0, [%o0 + %o5] ASI_M_FLUSH_PAGE
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sta %g0, [%o0 + %g1] ASI_M_FLUSH_PAGE
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sta %g0, [%o0 + %g2] ASI_M_FLUSH_PAGE
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sta %g0, [%o0 + %g3] ASI_M_FLUSH_PAGE
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andcc %o0, 0xffc, %g0
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sta %g0, [%o0 + %g4] ASI_M_FLUSH_PAGE
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bne 1b
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sta %g0, [%o0 + %g5] ASI_M_FLUSH_PAGE
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2:
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mov SRMMU_FAULT_STATUS, %g1
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retl
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lda [%g1] ASI_M_MMUREGS, %g0
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/* HyperSparc is IO cache coherent. */
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hypersparc_flush_page_for_dma:
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retl
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nop
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/* It was noted that at boot time a TLB flush all in a delay slot
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* can deliver an illegal instruction to the processor if the timing
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* is just right...
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*/
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hypersparc_flush_tlb_all:
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mov 0x400, %g1
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sta %g0, [%g1] ASI_M_FLUSH_PROBE
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retl
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nop
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hypersparc_flush_tlb_mm:
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mov SRMMU_CTX_REG, %g1
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ld [%o0 + AOFF_mm_context], %o1
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lda [%g1] ASI_M_MMUREGS, %g5
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#ifndef CONFIG_SMP
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cmp %o1, -1
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be hypersparc_flush_tlb_mm_out
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#endif
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mov 0x300, %g2
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sta %o1, [%g1] ASI_M_MMUREGS
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sta %g0, [%g2] ASI_M_FLUSH_PROBE
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hypersparc_flush_tlb_mm_out:
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retl
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sta %g5, [%g1] ASI_M_MMUREGS
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hypersparc_flush_tlb_range:
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ld [%o0 + VMA_VM_MM], %o0
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mov SRMMU_CTX_REG, %g1
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ld [%o0 + AOFF_mm_context], %o3
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lda [%g1] ASI_M_MMUREGS, %g5
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#ifndef CONFIG_SMP
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cmp %o3, -1
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be hypersparc_flush_tlb_range_out
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#endif
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sethi %hi(~((1 << PGDIR_SHIFT) - 1)), %o4
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sta %o3, [%g1] ASI_M_MMUREGS
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and %o1, %o4, %o1
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add %o1, 0x200, %o1
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sta %g0, [%o1] ASI_M_FLUSH_PROBE
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1:
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sub %o1, %o4, %o1
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cmp %o1, %o2
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blu,a 1b
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sta %g0, [%o1] ASI_M_FLUSH_PROBE
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hypersparc_flush_tlb_range_out:
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retl
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sta %g5, [%g1] ASI_M_MMUREGS
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hypersparc_flush_tlb_page:
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ld [%o0 + VMA_VM_MM], %o0
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mov SRMMU_CTX_REG, %g1
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ld [%o0 + AOFF_mm_context], %o3
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andn %o1, (PAGE_SIZE - 1), %o1
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#ifndef CONFIG_SMP
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cmp %o3, -1
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be hypersparc_flush_tlb_page_out
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#endif
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lda [%g1] ASI_M_MMUREGS, %g5
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sta %o3, [%g1] ASI_M_MMUREGS
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sta %g0, [%o1] ASI_M_FLUSH_PROBE
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hypersparc_flush_tlb_page_out:
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retl
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sta %g5, [%g1] ASI_M_MMUREGS
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__INIT
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/* High speed page clear/copy. */
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hypersparc_bzero_1page:
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/* NOTE: This routine has to be shorter than 40insns --jj */
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clr %g1
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mov 32, %g2
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mov 64, %g3
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mov 96, %g4
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mov 128, %g5
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mov 160, %g7
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mov 192, %o2
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mov 224, %o3
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mov 16, %o1
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1:
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stda %g0, [%o0 + %g0] ASI_M_BFILL
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stda %g0, [%o0 + %g2] ASI_M_BFILL
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stda %g0, [%o0 + %g3] ASI_M_BFILL
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stda %g0, [%o0 + %g4] ASI_M_BFILL
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stda %g0, [%o0 + %g5] ASI_M_BFILL
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stda %g0, [%o0 + %g7] ASI_M_BFILL
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stda %g0, [%o0 + %o2] ASI_M_BFILL
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stda %g0, [%o0 + %o3] ASI_M_BFILL
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subcc %o1, 1, %o1
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bne 1b
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add %o0, 256, %o0
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retl
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nop
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hypersparc_copy_1page:
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/* NOTE: This routine has to be shorter than 70insns --jj */
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sub %o1, %o0, %o2 ! difference
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mov 16, %g1
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1:
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sta %o0, [%o0 + %o2] ASI_M_BCOPY
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add %o0, 32, %o0
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sta %o0, [%o0 + %o2] ASI_M_BCOPY
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add %o0, 32, %o0
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sta %o0, [%o0 + %o2] ASI_M_BCOPY
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add %o0, 32, %o0
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sta %o0, [%o0 + %o2] ASI_M_BCOPY
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add %o0, 32, %o0
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sta %o0, [%o0 + %o2] ASI_M_BCOPY
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add %o0, 32, %o0
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sta %o0, [%o0 + %o2] ASI_M_BCOPY
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add %o0, 32, %o0
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sta %o0, [%o0 + %o2] ASI_M_BCOPY
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add %o0, 32, %o0
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sta %o0, [%o0 + %o2] ASI_M_BCOPY
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subcc %g1, 1, %g1
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bne 1b
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add %o0, 32, %o0
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retl
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nop
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.globl hypersparc_setup_blockops
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hypersparc_setup_blockops:
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sethi %hi(bzero_1page), %o0
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or %o0, %lo(bzero_1page), %o0
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sethi %hi(hypersparc_bzero_1page), %o1
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or %o1, %lo(hypersparc_bzero_1page), %o1
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sethi %hi(hypersparc_copy_1page), %o2
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or %o2, %lo(hypersparc_copy_1page), %o2
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ld [%o1], %o4
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1:
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add %o1, 4, %o1
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st %o4, [%o0]
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add %o0, 4, %o0
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cmp %o1, %o2
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bne 1b
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ld [%o1], %o4
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sethi %hi(__copy_1page), %o0
|
|
or %o0, %lo(__copy_1page), %o0
|
|
sethi %hi(hypersparc_setup_blockops), %o2
|
|
or %o2, %lo(hypersparc_setup_blockops), %o2
|
|
ld [%o1], %o4
|
|
1:
|
|
add %o1, 4, %o1
|
|
st %o4, [%o0]
|
|
add %o0, 4, %o0
|
|
cmp %o1, %o2
|
|
bne 1b
|
|
ld [%o1], %o4
|
|
sta %g0, [%g0] ASI_M_FLUSH_IWHOLE
|
|
retl
|
|
nop
|