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7403e87c13
The Glymur platform has four DisplayPort controllers. The hardware supports four streams (MST) per controller. However, on Glymur the first three controllers only have two streams wired to the display subsystem, while the fourth controller operates in single-stream mode. Add a dedicated clause for the Glymur compatible to require the register ranges for all four stream blocks, while allowing either one pixel clock (for the single-stream controller) or two pixel clocks (for the remaining controllers). Update the Glymur MDSS schema example by adding the missing p2, p3, mst2link and mst3link register blocks. Without these, the bindings validation fails. Also replace the made-up register addresses with the actual addresses from the first controller to match the SoC devicetree description. Cc: stable@vger.kernel.org # v6.19 Fixes:8f63bf9082("dt-bindings: display: msm: Document the Glymur DiplayPort controller") Fixes:1aee577bbc("dt-bindings: display: msm: Document the Glymur Mobile Display SubSystem") Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/708518/ Link: https://lore.kernel.org/r/20260303-glymur-fix-dp-bindings-reg-clocks-v4-1-1ebd9c7c2cee@oss.qualcomm.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
269 lines
8.2 KiB
YAML
269 lines
8.2 KiB
YAML
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/display/msm/qcom,glymur-mdss.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Glymur Display MDSS
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maintainers:
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- Abel Vesa <abel.vesa@linaro.org>
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description:
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Glymur MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like
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DPU display controller, DP interfaces, etc.
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$ref: /schemas/display/msm/mdss-common.yaml#
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properties:
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compatible:
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const: qcom,glymur-mdss
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clocks:
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items:
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- description: Display AHB
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- description: Display hf AXI
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- description: Display core
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iommus:
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maxItems: 1
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interconnects:
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items:
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- description: Interconnect path from mdp0 port to the data bus
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- description: Interconnect path from CPU to the reg bus
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interconnect-names:
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items:
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- const: mdp0-mem
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- const: cpu-cfg
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patternProperties:
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"^display-controller@[0-9a-f]+$":
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type: object
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additionalProperties: true
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properties:
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compatible:
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const: qcom,glymur-dpu
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"^displayport-controller@[0-9a-f]+$":
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type: object
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additionalProperties: true
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properties:
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compatible:
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const: qcom,glymur-dp
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"^phy@[0-9a-f]+$":
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type: object
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additionalProperties: true
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properties:
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compatible:
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const: qcom,glymur-dp-phy
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required:
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- compatible
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/interconnect/qcom,icc.h>
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#include <dt-bindings/interconnect/qcom,glymur-rpmh.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/phy/phy-qcom-qmp.h>
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#include <dt-bindings/power/qcom,rpmhpd.h>
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display-subsystem@ae00000 {
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compatible = "qcom,glymur-mdss";
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reg = <0x0ae00000 0x1000>;
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reg-names = "mdss";
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interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&dispcc_ahb_clk>,
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<&gcc_disp_hf_axi_clk>,
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<&dispcc_mdp_clk>;
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clock-names = "bus", "nrt_bus", "core";
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interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS
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&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
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<&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
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&config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
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interconnect-names = "mdp0-mem",
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"cpu-cfg";
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resets = <&disp_cc_mdss_core_bcr>;
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power-domains = <&mdss_gdsc>;
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iommus = <&apps_smmu 0x1c00 0x2>;
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interrupt-controller;
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#interrupt-cells = <1>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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display-controller@ae01000 {
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compatible = "qcom,glymur-dpu";
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reg = <0x0ae01000 0x8f000>,
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<0x0aeb0000 0x2008>;
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reg-names = "mdp", "vbif";
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clocks = <&gcc_axi_clk>,
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<&dispcc_ahb_clk>,
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<&dispcc_mdp_lut_clk>,
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<&dispcc_mdp_clk>,
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<&dispcc_mdp_vsync_clk>;
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clock-names = "nrt_bus",
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"iface",
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"lut",
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"core",
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"vsync";
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assigned-clocks = <&dispcc_mdp_vsync_clk>;
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assigned-clock-rates = <19200000>;
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operating-points-v2 = <&mdp_opp_table>;
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power-domains = <&rpmhpd RPMHPD_MMCX>;
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interrupt-parent = <&mdss>;
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interrupts = <0>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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dpu_intf1_out: endpoint {
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remote-endpoint = <&dsi0_in>;
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};
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};
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port@1 {
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reg = <1>;
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dpu_intf2_out: endpoint {
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remote-endpoint = <&dsi1_in>;
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};
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};
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};
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mdp_opp_table: opp-table {
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compatible = "operating-points-v2";
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opp-200000000 {
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opp-hz = /bits/ 64 <200000000>;
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required-opps = <&rpmhpd_opp_low_svs>;
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};
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opp-325000000 {
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opp-hz = /bits/ 64 <325000000>;
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required-opps = <&rpmhpd_opp_svs>;
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};
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opp-375000000 {
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opp-hz = /bits/ 64 <375000000>;
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required-opps = <&rpmhpd_opp_svs_l1>;
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};
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opp-514000000 {
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opp-hz = /bits/ 64 <514000000>;
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required-opps = <&rpmhpd_opp_nom>;
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};
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};
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};
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displayport-controller@af54000 {
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compatible = "qcom,glymur-dp";
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reg = <0xaf54000 0x200>,
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<0xaf54200 0x200>,
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<0xaf55000 0xc00>,
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<0xaf56000 0x400>,
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<0xaf57000 0x400>,
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<0xaf58000 0x400>,
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<0xaf59000 0x400>,
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<0xaf5a000 0x600>,
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<0xaf5b000 0x600>;
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interrupt-parent = <&mdss>;
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interrupts = <12>;
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clocks = <&dispcc_mdss_ahb_clk>,
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<&dispcc_dptx0_aux_clk>,
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<&dispcc_dptx0_link_clk>,
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<&dispcc_dptx0_link_intf_clk>,
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<&dispcc_dptx0_pixel0_clk>,
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<&dispcc_dptx0_pixel1_clk>;
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clock-names = "core_iface",
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"core_aux",
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"ctrl_link",
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"ctrl_link_iface",
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"stream_pixel",
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"stream_1_pixel";
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assigned-clocks = <&dispcc_mdss_dptx0_link_clk_src>,
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<&dispcc_mdss_dptx0_pixel0_clk_src>,
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<&dispcc_mdss_dptx0_pixel1_clk_src>;
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assigned-clock-parents = <&usb_1_ss0_qmpphy QMP_USB43DP_DP_LINK_CLK>,
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<&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
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<&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
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operating-points-v2 = <&mdss_dp0_opp_table>;
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power-domains = <&rpmhpd RPMHPD_MMCX>;
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phys = <&usb_1_ss0_qmpphy QMP_USB43DP_DP_PHY>;
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phy-names = "dp";
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#sound-dai-cells = <0>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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mdss_dp0_in: endpoint {
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remote-endpoint = <&mdss_intf0_out>;
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};
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};
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port@1 {
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reg = <1>;
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mdss_dp0_out: endpoint {
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};
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};
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};
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mdss_dp0_opp_table: opp-table {
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compatible = "operating-points-v2";
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opp-160000000 {
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opp-hz = /bits/ 64 <160000000>;
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required-opps = <&rpmhpd_opp_low_svs>;
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};
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opp-270000000 {
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opp-hz = /bits/ 64 <270000000>;
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required-opps = <&rpmhpd_opp_svs>;
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};
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opp-540000000 {
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opp-hz = /bits/ 64 <540000000>;
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required-opps = <&rpmhpd_opp_svs_l1>;
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};
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opp-810000000 {
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opp-hz = /bits/ 64 <810000000>;
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required-opps = <&rpmhpd_opp_nom>;
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};
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};
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};
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};
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...
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