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7403e87c13
The Glymur platform has four DisplayPort controllers. The hardware supports four streams (MST) per controller. However, on Glymur the first three controllers only have two streams wired to the display subsystem, while the fourth controller operates in single-stream mode. Add a dedicated clause for the Glymur compatible to require the register ranges for all four stream blocks, while allowing either one pixel clock (for the single-stream controller) or two pixel clocks (for the remaining controllers). Update the Glymur MDSS schema example by adding the missing p2, p3, mst2link and mst3link register blocks. Without these, the bindings validation fails. Also replace the made-up register addresses with the actual addresses from the first controller to match the SoC devicetree description. Cc: stable@vger.kernel.org # v6.19 Fixes:8f63bf9082("dt-bindings: display: msm: Document the Glymur DiplayPort controller") Fixes:1aee577bbc("dt-bindings: display: msm: Document the Glymur Mobile Display SubSystem") Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/708518/ Link: https://lore.kernel.org/r/20260303-glymur-fix-dp-bindings-reg-clocks-v4-1-1ebd9c7c2cee@oss.qualcomm.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
392 lines
9.2 KiB
YAML
392 lines
9.2 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/display/msm/dp-controller.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: MSM Display Port Controller
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maintainers:
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- Kuogee Hsieh <quic_khsieh@quicinc.com>
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- Abhinav Kumar <quic_abhinavk@quicinc.com>
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description: |
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Device tree bindings for DisplayPort host controller for MSM targets
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that are compatible with VESA DisplayPort interface specification.
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properties:
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compatible:
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oneOf:
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- enum:
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- qcom,glymur-dp
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- qcom,sa8775p-dp
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- qcom,sc7180-dp
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- qcom,sc7280-dp
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- qcom,sc7280-edp
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- qcom,sc8180x-dp
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- qcom,sc8180x-edp
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- qcom,sc8280xp-dp
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- qcom,sc8280xp-edp
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- qcom,sdm845-dp
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- qcom,sm8350-dp
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- qcom,sm8650-dp
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- qcom,x1e80100-dp
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- items:
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- enum:
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- qcom,qcs8300-dp
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- const: qcom,sa8775p-dp
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- items:
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- enum:
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- qcom,sm6350-dp
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- const: qcom,sc7180-dp
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# deprecated entry for compatibility with old DT
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- items:
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- enum:
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- qcom,sm6350-dp
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- const: qcom,sm8350-dp
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deprecated: true
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- items:
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- enum:
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- qcom,sar2130p-dp
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- qcom,sm7150-dp
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- qcom,sm8150-dp
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- qcom,sm8250-dp
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- qcom,sm8450-dp
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- qcom,sm8550-dp
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- const: qcom,sm8350-dp
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- items:
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- enum:
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- qcom,sm6150-dp
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- const: qcom,sm8150-dp
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- const: qcom,sm8350-dp
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- items:
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- enum:
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- qcom,sm8750-dp
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- const: qcom,sm8650-dp
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reg:
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minItems: 4
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items:
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- description: ahb register block
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- description: aux register block
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- description: link register block
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- description: p0 register block
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- description: p1 register block
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- description: p2 register block
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- description: p3 register block
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- description: mst2link register block
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- description: mst3link register block
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interrupts:
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maxItems: 1
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clocks:
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minItems: 5
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items:
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- description: AHB clock to enable register access
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- description: Display Port AUX clock
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- description: Display Port Link clock
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- description: Link interface clock between DP and PHY
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- description: Display Port stream 0 Pixel clock
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- description: Display Port stream 1 Pixel clock
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- description: Display Port stream 2 Pixel clock
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- description: Display Port stream 3 Pixel clock
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clock-names:
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minItems: 5
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items:
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- const: core_iface
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- const: core_aux
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- const: ctrl_link
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- const: ctrl_link_iface
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- const: stream_pixel
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- const: stream_1_pixel
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- const: stream_2_pixel
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- const: stream_3_pixel
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phys:
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maxItems: 1
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phy-names:
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items:
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- const: dp
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operating-points-v2: true
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opp-table:
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type: object
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power-domains:
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maxItems: 1
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aux-bus:
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$ref: /schemas/display/dp-aux-bus.yaml#
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data-lanes:
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$ref: /schemas/types.yaml#/definitions/uint32-array
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deprecated: true
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minItems: 1
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maxItems: 4
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items:
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maximum: 3
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"#sound-dai-cells":
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const: 0
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vdda-0p9-supply:
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deprecated: true
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vdda-1p2-supply:
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deprecated: true
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ports:
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$ref: /schemas/graph.yaml#/properties/ports
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properties:
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port@0:
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$ref: /schemas/graph.yaml#/properties/port
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description: Input endpoint of the controller
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port@1:
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$ref: /schemas/graph.yaml#/$defs/port-base
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unevaluatedProperties: false
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description: Output endpoint of the controller
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properties:
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endpoint:
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$ref: /schemas/media/video-interfaces.yaml#
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unevaluatedProperties: false
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properties:
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data-lanes:
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minItems: 1
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maxItems: 4
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items:
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enum: [ 0, 1, 2, 3 ]
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link-frequencies:
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minItems: 1
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maxItems: 4
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items:
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enum: [ 1620000000, 2700000000, 5400000000, 8100000000 ]
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required:
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- port@0
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- port@1
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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- clock-names
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- phys
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- phy-names
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- power-domains
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- ports
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allOf:
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# AUX BUS does not exist on DP controllers
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# Audio output also is present only on DP output
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- if:
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properties:
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compatible:
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contains:
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enum:
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- qcom,sc7280-edp
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- qcom,sc8180x-edp
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- qcom,sc8280xp-edp
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then:
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properties:
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"#sound-dai-cells": false
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else:
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if:
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properties:
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compatible:
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contains:
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enum:
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- qcom,glymur-dp
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- qcom,sa8775p-dp
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- qcom,x1e80100-dp
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then:
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$ref: /schemas/sound/dai-common.yaml#
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oneOf:
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- required:
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- aux-bus
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- required:
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- "#sound-dai-cells"
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else:
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properties:
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aux-bus: false
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required:
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- "#sound-dai-cells"
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- if:
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properties:
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compatible:
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contains:
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enum:
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# these platforms support SST only
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- qcom,sc7180-dp
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- qcom,sc7280-dp
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- qcom,sc7280-edp
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- qcom,sc8180x-edp
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- qcom,sc8280xp-edp
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then:
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properties:
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reg:
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minItems: 5
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maxItems: 5
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clocks:
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minItems: 5
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maxItems: 5
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clocks-names:
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minItems: 5
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maxItems: 5
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- if:
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properties:
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compatible:
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contains:
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enum:
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# these platforms support 2 streams MST on some interfaces,
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# others are SST only
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- qcom,sc8280xp-dp
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- qcom,x1e80100-dp
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then:
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properties:
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reg:
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minItems: 5
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maxItems: 5
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clocks:
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minItems: 5
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maxItems: 6
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clocks-names:
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minItems: 5
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maxItems: 6
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- if:
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properties:
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compatible:
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contains:
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# 2 streams MST
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enum:
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- qcom,sc8180x-dp
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- qcom,sdm845-dp
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- qcom,sm8350-dp
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- qcom,sm8650-dp
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then:
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properties:
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reg:
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minItems: 5
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maxItems: 5
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clocks:
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minItems: 6
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maxItems: 6
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clocks-names:
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minItems: 6
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maxItems: 6
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- if:
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properties:
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compatible:
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contains:
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enum:
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# these platforms support 4 stream MST on first DP,
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# 2 streams MST on the second one.
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- qcom,sa8775p-dp
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then:
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properties:
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reg:
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minItems: 9
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maxItems: 9
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clocks:
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minItems: 6
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maxItems: 8
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clocks-names:
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minItems: 6
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maxItems: 8
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- if:
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properties:
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compatible:
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contains:
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enum:
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# these platforms support 2 streams MST on some interfaces,
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# others are SST only, but all controllers have 4 ports
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- qcom,glymur-dp
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then:
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properties:
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reg:
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minItems: 9
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maxItems: 9
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clocks:
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minItems: 5
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maxItems: 6
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clocks-names:
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minItems: 5
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maxItems: 6
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/qcom,dispcc-sc7180.h>
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#include <dt-bindings/power/qcom-rpmpd.h>
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displayport-controller@ae90000 {
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compatible = "qcom,sc7180-dp";
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reg = <0xae90000 0x200>,
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<0xae90200 0x200>,
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<0xae90400 0xc00>,
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<0xae91000 0x400>,
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<0xae91400 0x400>;
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interrupt-parent = <&mdss>;
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interrupts = <12>;
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clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
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<&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
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<&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
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<&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
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<&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
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clock-names = "core_iface", "core_aux",
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"ctrl_link",
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"ctrl_link_iface", "stream_pixel";
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assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
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<&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
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assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
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phys = <&dp_phy>;
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phy-names = "dp";
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#sound-dai-cells = <0>;
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power-domains = <&rpmhpd SC7180_CX>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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endpoint {
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remote-endpoint = <&dpu_intf0_out>;
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};
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};
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port@1 {
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reg = <1>;
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endpoint {
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remote-endpoint = <&typec>;
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data-lanes = <0 1>;
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link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>;
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};
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};
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};
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};
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...
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