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5422570c00
This patch implements the "ethtool --set-mm" callback to trigger the
frame preemption verification handshake.
Uses the MAC Merge Software Verification (mmsv) mechanism in ethtool
to perform the verification handshake for igc.
The structure fpe.mmsv is set by mmsv in ethtool and should remain
read-only for the driver.
Other mmsv callbacks:
a) configure_tx() -> not used yet at this point
- igc lacks registers to configure FPE in the transmit direction, so
this API is not utilized for now. When igc supports preemptible queue,
driver will use this API to manage its configuration.
b) configure_pmac() -> not used
- this callback dynamically controls pmac_enabled at runtime. For
example, mmsv calls configure_pmac() and disables pmac_enabled when
the link partner goes down, even if the user previously enabled it.
The intention is to save power but it is not feasible in igc
because it causes an endless adapter reset loop:
1) Board A and Board B complete the verification handshake. Tx mode
register for both boards are in TSN mode.
2) Board B link goes down.
On Board A:
3) mmsv calls configure_pmac() with pmac_enabled = false.
4) configure_pmac() in igc updates a new field based on pmac_enabled.
Driver uses this field in igc_tsn_new_flags() to indicate that the
user enabled/disabled FPE.
5) configure_pmac() in igc calls igc_tsn_offload_apply() to check
whether an adapter reset is needed. Calls existing logic in
igc_tsn_will_tx_mode_change() and igc_tsn_new_flags().
6) Since pmac_enabled is now disabled and no other TSN feature is
active, igc_tsn_will_tx_mode_change() evaluates to true because Tx
mode will switch from TSN to Legacy.
7) Driver resets the adapter.
8) Registers are set, and Tx mode switches to Legacy.
9) When link partner is up, steps 3-8 repeat, but this time with
pmac_enabled = true, reactivating TSN.
igc_tsn_will_tx_mode_change() evaluates to true again, since Tx
mode will switch from Legacy to TSN.
10) Driver resets the adapter.
11) Adapter reset completes, registers are set, and Tx mode switches to
TSN.
On Board B:
12) Adapter reset on Board A at step 10 causes it to detect its link
partner as down.
13) Repeats steps 3-8.
14) Once reset adapter on Board A is completed at step 11, it detects
its link partner as up.
15) Repeats steps 9-11.
- this cycle repeats indefinitely. To avoid this issue, igc only uses
mmsv.pmac_enabled to track whether FPE is enabled or disabled.
Co-developed-by: Vinicius Costa Gomes <vinicius.gomes@intel.com>
Signed-off-by: Vinicius Costa Gomes <vinicius.gomes@intel.com>
Co-developed-by: Choong Yong Liang <yong.liang.choong@linux.intel.com>
Signed-off-by: Choong Yong Liang <yong.liang.choong@linux.intel.com>
Co-developed-by: Chwee-Lin Choong <chwee.lin.choong@intel.com>
Signed-off-by: Chwee-Lin Choong <chwee.lin.choong@intel.com>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: Faizal Rahim <faizal.abdul.rahim@linux.intel.com>
Tested-by: Mor Bar-Gabay <morx.bar.gabay@intel.com>
Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
108 lines
3.6 KiB
C
108 lines
3.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright (c) 2018 Intel Corporation */
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#ifndef _IGC_BASE_H_
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#define _IGC_BASE_H_
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/* forward declaration */
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void igc_rx_fifo_flush_base(struct igc_hw *hw);
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void igc_power_down_phy_copper_base(struct igc_hw *hw);
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bool igc_is_device_id_i225(struct igc_hw *hw);
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bool igc_is_device_id_i226(struct igc_hw *hw);
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/* Transmit Descriptor - Advanced */
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union igc_adv_tx_desc {
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struct {
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__le64 buffer_addr; /* Address of descriptor's data buf */
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__le32 cmd_type_len;
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__le32 olinfo_status;
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} read;
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struct {
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__le64 rsvd; /* Reserved */
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__le32 nxtseq_seed;
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__le32 status;
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} wb;
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};
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/* Context descriptors */
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struct igc_adv_tx_context_desc {
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__le32 vlan_macip_lens;
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__le32 launch_time;
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__le32 type_tucmd_mlhl;
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__le32 mss_l4len_idx;
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};
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/* Adv Transmit Descriptor Config Masks */
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#define IGC_ADVTXD_MAC_TSTAMP 0x00080000 /* IEEE1588 Timestamp packet */
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#define IGC_ADVTXD_TSTAMP_REG_1 0x00010000 /* Select register 1 for timestamp */
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#define IGC_ADVTXD_TSTAMP_REG_2 0x00020000 /* Select register 2 for timestamp */
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#define IGC_ADVTXD_TSTAMP_REG_3 0x00030000 /* Select register 3 for timestamp */
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#define IGC_ADVTXD_TSTAMP_TIMER_1 0x00010000 /* Select timer 1 for timestamp */
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#define IGC_ADVTXD_TSTAMP_TIMER_2 0x00020000 /* Select timer 2 for timestamp */
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#define IGC_ADVTXD_TSTAMP_TIMER_3 0x00030000 /* Select timer 3 for timestamp */
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#define IGC_ADVTXD_DTYP_CTXT 0x00200000 /* Advanced Context Descriptor */
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#define IGC_ADVTXD_DTYP_DATA 0x00300000 /* Advanced Data Descriptor */
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#define IGC_ADVTXD_DCMD_EOP 0x01000000 /* End of Packet */
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#define IGC_ADVTXD_DCMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */
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#define IGC_ADVTXD_DCMD_RS 0x08000000 /* Report Status */
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#define IGC_ADVTXD_DCMD_DEXT 0x20000000 /* Descriptor extension (1=Adv) */
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#define IGC_ADVTXD_DCMD_VLE 0x40000000 /* VLAN pkt enable */
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#define IGC_ADVTXD_DCMD_TSE 0x80000000 /* TCP Seg enable */
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#define IGC_ADVTXD_PAYLEN_MASK 0XFFFFC000 /* Adv desc PAYLEN mask */
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#define IGC_ADVTXD_PAYLEN_SHIFT 14 /* Adv desc PAYLEN shift */
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#define IGC_RAR_ENTRIES 16
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/* Receive Descriptor - Advanced */
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union igc_adv_rx_desc {
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struct {
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__le64 pkt_addr; /* Packet buffer address */
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__le64 hdr_addr; /* Header buffer address */
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} read;
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struct {
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struct {
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union {
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__le32 data;
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struct {
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__le16 pkt_info; /*RSS type, Pkt type*/
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/* Split Header, header buffer len */
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__le16 hdr_info;
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} hs_rss;
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} lo_dword;
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union {
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__le32 rss; /* RSS Hash */
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struct {
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__le16 ip_id; /* IP id */
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__le16 csum; /* Packet Checksum */
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} csum_ip;
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} hi_dword;
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} lower;
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struct {
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__le32 status_error; /* ext status/error */
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__le16 length; /* Packet length */
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__le16 vlan; /* VLAN tag */
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} upper;
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} wb; /* writeback */
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};
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/* Additional Transmit Descriptor Control definitions */
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#define IGC_TXDCTL_QUEUE_ENABLE 0x02000000 /* Ena specific Tx Queue */
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#define IGC_TXDCTL_SWFLUSH 0x04000000 /* Transmit Software Flush */
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/* Additional Receive Descriptor Control definitions */
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#define IGC_RXDCTL_QUEUE_ENABLE 0x02000000 /* Ena specific Rx Queue */
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#define IGC_RXDCTL_SWFLUSH 0x04000000 /* Receive Software Flush */
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/* SRRCTL bit definitions */
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#define IGC_SRRCTL_BSIZEPKT_MASK GENMASK(6, 0)
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#define IGC_SRRCTL_BSIZEPKT(x) FIELD_PREP(IGC_SRRCTL_BSIZEPKT_MASK, \
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(x) / 1024) /* in 1 KB resolution */
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#define IGC_SRRCTL_BSIZEHDR_MASK GENMASK(13, 8)
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#define IGC_SRRCTL_BSIZEHDR(x) FIELD_PREP(IGC_SRRCTL_BSIZEHDR_MASK, \
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(x) / 64) /* in 64 bytes resolution */
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#define IGC_SRRCTL_DESCTYPE_MASK GENMASK(27, 25)
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#define IGC_SRRCTL_DESCTYPE_ADV_ONEBUF FIELD_PREP(IGC_SRRCTL_DESCTYPE_MASK, 1)
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#endif /* _IGC_BASE_H */
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