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linux/drivers/gpu/drm/nouveau/include/nvkm/engine/falcon.h
Ben Skeggs 0e44c21708 drm/nouveau/flcn: new code to load+boot simple HS FWs (VPR scrubber)
Adds the start of common interfaces to load and boot the HS binaries
provided by NVIDIA that enable the usage of GR.

ACR already handles most of this, but it's very much tied into ACR's
init process, and there's other code that could benefit from reusing
a lot of this stuff too (ie. VBIOS DEVINIT/PreOS, VPR scrubber).

The VPR scrubber code is fairly independent, and a good first target.

- adds better debug output to fw loading process, to ease bring-up/debug

v2:
- whitespace, 0->false

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
2022-11-09 10:44:58 +10:00

132 lines
3.2 KiB
C

/* SPDX-License-Identifier: MIT */
#ifndef __NVKM_FLCNEN_H__
#define __NVKM_FLCNEN_H__
#define nvkm_falcon(p) container_of((p), struct nvkm_falcon, engine)
#include <core/engine.h>
struct nvkm_fifo_chan;
enum nvkm_falcon_dmaidx {
FALCON_DMAIDX_UCODE = 0,
FALCON_DMAIDX_VIRT = 1,
FALCON_DMAIDX_PHYS_VID = 2,
FALCON_DMAIDX_PHYS_SYS_COH = 3,
FALCON_DMAIDX_PHYS_SYS_NCOH = 4,
FALCON_SEC2_DMAIDX_UCODE = 6,
};
struct nvkm_falcon {
const struct nvkm_falcon_func *func;
struct nvkm_subdev *owner;
const char *name;
u32 addr;
struct mutex mutex;
struct mutex dmem_mutex;
bool oneinit;
struct nvkm_subdev *user;
u8 version;
u8 secret;
bool debug;
struct nvkm_memory *core;
bool external;
struct {
u32 limit;
u32 *data;
u32 size;
u8 ports;
} code;
struct {
u32 limit;
u32 *data;
u32 size;
u8 ports;
} data;
struct nvkm_engine engine;
};
int nvkm_falcon_get(struct nvkm_falcon *, struct nvkm_subdev *);
void nvkm_falcon_put(struct nvkm_falcon *, struct nvkm_subdev *);
int nvkm_falcon_new_(const struct nvkm_falcon_func *, struct nvkm_device *,
enum nvkm_subdev_type, int inst, bool enable, u32 addr, struct nvkm_engine **);
struct nvkm_falcon_func {
int (*disable)(struct nvkm_falcon *);
int (*enable)(struct nvkm_falcon *);
bool reset_pmc;
int (*reset_eng)(struct nvkm_falcon *);
int (*reset_wait_mem_scrubbing)(struct nvkm_falcon *);
u32 debug;
const struct nvkm_falcon_func_pio *imem_pio;
const struct nvkm_falcon_func_pio *dmem_pio;
struct {
u32 *data;
u32 size;
} code;
struct {
u32 *data;
u32 size;
} data;
void (*init)(struct nvkm_falcon *);
void (*intr)(struct nvkm_falcon *, struct nvkm_chan *);
u32 fbif;
void (*load_imem)(struct nvkm_falcon *, void *, u32, u32, u16, u8, bool);
void (*load_dmem)(struct nvkm_falcon *, void *, u32, u32, u8);
void (*read_dmem)(struct nvkm_falcon *, u32, u32, u8, void *);
u32 emem_addr;
void (*bind_context)(struct nvkm_falcon *, struct nvkm_memory *);
int (*wait_for_halt)(struct nvkm_falcon *, u32);
int (*clear_interrupt)(struct nvkm_falcon *, u32);
void (*set_start_addr)(struct nvkm_falcon *, u32 start_addr);
void (*start)(struct nvkm_falcon *);
struct {
u32 head;
u32 tail;
u32 stride;
} cmdq, msgq;
struct nvkm_sclass sclass[];
};
static inline u32
nvkm_falcon_rd32(struct nvkm_falcon *falcon, u32 addr)
{
return nvkm_rd32(falcon->owner->device, falcon->addr + addr);
}
static inline void
nvkm_falcon_wr32(struct nvkm_falcon *falcon, u32 addr, u32 data)
{
nvkm_wr32(falcon->owner->device, falcon->addr + addr, data);
}
static inline u32
nvkm_falcon_mask(struct nvkm_falcon *falcon, u32 addr, u32 mask, u32 val)
{
struct nvkm_device *device = falcon->owner->device;
return nvkm_mask(device, falcon->addr + addr, mask, val);
}
void nvkm_falcon_load_imem(struct nvkm_falcon *, void *, u32, u32, u16, u8,
bool);
void nvkm_falcon_load_dmem(struct nvkm_falcon *, void *, u32, u32, u8);
void nvkm_falcon_read_dmem(struct nvkm_falcon *, u32, u32, u8, void *);
void nvkm_falcon_bind_context(struct nvkm_falcon *, struct nvkm_memory *);
void nvkm_falcon_set_start_addr(struct nvkm_falcon *, u32);
void nvkm_falcon_start(struct nvkm_falcon *);
int nvkm_falcon_wait_for_halt(struct nvkm_falcon *, u32);
int nvkm_falcon_clear_interrupt(struct nvkm_falcon *, u32);
#endif