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git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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8279a8dacf
Correct the hardware revision check comment in the QT2025 driver. The revision value was documented as 0x3b instead of the correct 0xb3, which matches the actual comparison logic in the code. Reviewed-by: FUJITA Tomonori <fujita.tomonori@gmail.com> Signed-off-by: Charalampos Mitrodimas <charmitro@posteo.net> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Reviewed-by: Trevor Gross <tmgross@umich.edu> Link: https://patch.msgid.link/20250219-qt2025-comment-fix-v2-1-029f67696516@posteo.net Signed-off-by: Jakub Kicinski <kuba@kernel.org>
104 lines
3.8 KiB
Rust
104 lines
3.8 KiB
Rust
// SPDX-License-Identifier: GPL-2.0
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// Copyright (C) Tehuti Networks Ltd.
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// Copyright (C) 2024 FUJITA Tomonori <fujita.tomonori@gmail.com>
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//! Applied Micro Circuits Corporation QT2025 PHY driver
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//!
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//! This driver is based on the vendor driver `QT2025_phy.c`. This source
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//! and firmware can be downloaded on the EN-9320SFP+ support site.
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//!
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//! The QT2025 PHY integrates an Intel 8051 micro-controller.
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use kernel::c_str;
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use kernel::error::code;
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use kernel::firmware::Firmware;
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use kernel::net::phy::{
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self,
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reg::{Mmd, C45},
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Driver,
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};
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use kernel::prelude::*;
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use kernel::sizes::{SZ_16K, SZ_8K};
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kernel::module_phy_driver! {
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drivers: [PhyQT2025],
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device_table: [
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phy::DeviceId::new_with_driver::<PhyQT2025>(),
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],
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name: "qt2025_phy",
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author: "FUJITA Tomonori <fujita.tomonori@gmail.com>",
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description: "AMCC QT2025 PHY driver",
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license: "GPL",
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firmware: ["qt2025-2.0.3.3.fw"],
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}
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struct PhyQT2025;
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#[vtable]
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impl Driver for PhyQT2025 {
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const NAME: &'static CStr = c_str!("QT2025 10Gpbs SFP+");
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const PHY_DEVICE_ID: phy::DeviceId = phy::DeviceId::new_with_exact_mask(0x0043a400);
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fn probe(dev: &mut phy::Device) -> Result<()> {
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// Check the hardware revision code.
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// Only 0xb3 works with this driver and firmware.
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let hw_rev = dev.read(C45::new(Mmd::PMAPMD, 0xd001))?;
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if (hw_rev >> 8) != 0xb3 {
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return Err(code::ENODEV);
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}
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// `MICRO_RESETN`: hold the micro-controller in reset while configuring.
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dev.write(C45::new(Mmd::PMAPMD, 0xc300), 0x0000)?;
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// `SREFCLK_FREQ`: configure clock frequency of the micro-controller.
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dev.write(C45::new(Mmd::PMAPMD, 0xc302), 0x0004)?;
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// Non loopback mode.
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dev.write(C45::new(Mmd::PMAPMD, 0xc319), 0x0038)?;
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// `CUS_LAN_WAN_CONFIG`: select between LAN and WAN (WIS) mode.
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dev.write(C45::new(Mmd::PMAPMD, 0xc31a), 0x0098)?;
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// The following writes use standardized registers (3.38 through
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// 3.41 5/10/25GBASE-R PCS test pattern seed B) for something else.
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// We don't know what.
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dev.write(C45::new(Mmd::PCS, 0x0026), 0x0e00)?;
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dev.write(C45::new(Mmd::PCS, 0x0027), 0x0893)?;
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dev.write(C45::new(Mmd::PCS, 0x0028), 0xa528)?;
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dev.write(C45::new(Mmd::PCS, 0x0029), 0x0003)?;
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// Configure transmit and recovered clock.
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dev.write(C45::new(Mmd::PMAPMD, 0xa30a), 0x06e1)?;
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// `MICRO_RESETN`: release the micro-controller from the reset state.
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dev.write(C45::new(Mmd::PMAPMD, 0xc300), 0x0002)?;
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// The micro-controller will start running from the boot ROM.
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dev.write(C45::new(Mmd::PCS, 0xe854), 0x00c0)?;
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let fw = Firmware::request(c_str!("qt2025-2.0.3.3.fw"), dev.as_ref())?;
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if fw.data().len() > SZ_16K + SZ_8K {
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return Err(code::EFBIG);
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}
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// The 24kB of program memory space is accessible by MDIO.
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// The first 16kB of memory is located in the address range 3.8000h - 3.BFFFh.
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// The next 8kB of memory is located at 4.8000h - 4.9FFFh.
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let mut dst_offset = 0;
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let mut dst_mmd = Mmd::PCS;
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for (src_idx, val) in fw.data().iter().enumerate() {
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if src_idx == SZ_16K {
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// Start writing to the next register with no offset
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dst_offset = 0;
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dst_mmd = Mmd::PHYXS;
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}
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dev.write(C45::new(dst_mmd, 0x8000 + dst_offset), (*val).into())?;
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dst_offset += 1;
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}
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// The micro-controller will start running from SRAM.
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dev.write(C45::new(Mmd::PCS, 0xe854), 0x0040)?;
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// TODO: sleep here until the hw becomes ready.
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Ok(())
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}
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fn read_status(dev: &mut phy::Device) -> Result<u16> {
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dev.genphy_read_status::<C45>()
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}
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}
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