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git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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a5ea53da65
Add a new hwprobe key "RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0" which allows userspace to probe for the new RISCV_ISA_VENDOR_EXT_XTHEADVECTOR vendor extension. This new key will allow userspace code to probe for which thead vendor extensions are supported. This API is modeled to be consistent with RISCV_HWPROBE_KEY_IMA_EXT_0. The bitmask returned will have each bit corresponding to a supported thead vendor extension of the cpumask set. Just like RISCV_HWPROBE_KEY_IMA_EXT_0, this allows a userspace program to determine all of the supported thead vendor extensions in one call. Signed-off-by: Charlie Jenkins <charlie@rivosinc.com> Reviewed-by: Evan Green <evan@rivosinc.com> Tested-by: Yangyu Chen <cyy@cyyself.name> Link: https://lore.kernel.org/r/20241113-xtheadvector-v11-10-236c22791ef9@rivosinc.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
44 lines
913 B
C
44 lines
913 B
C
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
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/*
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* Copyright 2023-2024 Rivos, Inc
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*/
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#ifndef _ASM_HWPROBE_H
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#define _ASM_HWPROBE_H
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#include <uapi/asm/hwprobe.h>
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#define RISCV_HWPROBE_MAX_KEY 11
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static inline bool riscv_hwprobe_key_is_valid(__s64 key)
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{
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return key >= 0 && key <= RISCV_HWPROBE_MAX_KEY;
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}
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static inline bool hwprobe_key_is_bitmask(__s64 key)
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{
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switch (key) {
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case RISCV_HWPROBE_KEY_BASE_BEHAVIOR:
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case RISCV_HWPROBE_KEY_IMA_EXT_0:
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case RISCV_HWPROBE_KEY_CPUPERF_0:
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case RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0:
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return true;
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}
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return false;
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}
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static inline bool riscv_hwprobe_pair_cmp(struct riscv_hwprobe *pair,
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struct riscv_hwprobe *other_pair)
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{
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if (pair->key != other_pair->key)
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return false;
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if (hwprobe_key_is_bitmask(pair->key))
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return (pair->value & other_pair->value) == other_pair->value;
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return pair->value == other_pair->value;
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}
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#endif
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