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78aa7d0d9b
Move QCS404 PCIe devices from qcom,pcie.yaml binding to a dedicated file to make reviewing and maintenance easier. New schema is equivalent to the old one with few changes: - Adding a required compatible, which is actually redundant. - Drop the really obvious comments next to clock/reg/reset-names items. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20251217-dt-bindings-pci-qcom-v2-4-873721599754@oss.qualcomm.com
132 lines
3.4 KiB
YAML
132 lines
3.4 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pci/qcom,pcie-qcs404.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm QCS404 PCI Express Root Complex
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maintainers:
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- Bjorn Andersson <andersson@kernel.org>
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- Manivannan Sadhasivam <mani@kernel.org>
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properties:
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compatible:
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enum:
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- qcom,pcie-qcs404
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reg:
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maxItems: 4
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reg-names:
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items:
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- const: dbi
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- const: elbi
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- const: parf
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- const: config
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clocks:
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maxItems: 4
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clock-names:
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items:
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- const: iface # AHB clock
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- const: aux
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- const: master_bus # AXI Master clock
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- const: slave_bus # AXI Slave clock
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interrupts:
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maxItems: 1
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interrupt-names:
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items:
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- const: msi
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resets:
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maxItems: 6
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reset-names:
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items:
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- const: axi_m # AXI Master reset
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- const: axi_s # AXI Slave reset
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- const: axi_m_sticky # AXI Master Sticky reset
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- const: pipe_sticky
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- const: pwr
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- const: ahb
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required:
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- resets
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- reset-names
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allOf:
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- $ref: qcom,pcie-common.yaml#
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,gcc-qcs404.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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pcie@10000000 {
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compatible = "qcom,pcie-qcs404";
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reg = <0x10000000 0xf1d>,
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<0x10000f20 0xa8>,
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<0x07780000 0x2000>,
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<0x10001000 0x2000>;
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reg-names = "dbi", "elbi", "parf", "config";
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ranges = <0x81000000 0x0 0x00000000 0x10003000 0x0 0x00010000>, /* I/O */
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<0x82000000 0x0 0x10013000 0x10013000 0x0 0x007ed000>; /* memory */
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device_type = "pci";
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linux,pci-domain = <0>;
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bus-range = <0x00 0xff>;
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num-lanes = <1>;
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#address-cells = <3>;
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#size-cells = <2>;
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clocks = <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
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<&gcc GCC_PCIE_0_AUX_CLK>,
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<&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
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<&gcc GCC_PCIE_0_SLV_AXI_CLK>;
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clock-names = "iface", "aux", "master_bus", "slave_bus";
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interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "msi";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0x7>;
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interrupt-map = <0 0 0 1 &intc GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
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<0 0 0 2 &intc GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
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<0 0 0 3 &intc GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
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<0 0 0 4 &intc GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
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phys = <&pcie_phy>;
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phy-names = "pciephy";
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perst-gpios = <&tlmm 43 GPIO_ACTIVE_LOW>;
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resets = <&gcc GCC_PCIE_0_AXI_MASTER_ARES>,
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<&gcc GCC_PCIE_0_AXI_SLAVE_ARES>,
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<&gcc GCC_PCIE_0_AXI_MASTER_STICKY_ARES>,
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<&gcc GCC_PCIE_0_CORE_STICKY_ARES>,
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<&gcc GCC_PCIE_0_BCR>,
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<&gcc GCC_PCIE_0_AHB_ARES>;
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reset-names = "axi_m",
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"axi_s",
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"axi_m_sticky",
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"pipe_sticky",
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"pwr",
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"ahb";
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pcie@0 {
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device_type = "pci";
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reg = <0x0 0x0 0x0 0x0 0x0>;
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bus-range = <0x01 0xff>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges;
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};
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};
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