mirror of
git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
synced 2026-03-22 07:27:12 +08:00
6044a1ee9d
Pull devicetree updates from Rob Herring:
"DT bindings:
- Convert lattice,ice40-fpga-mgr, apm,xgene-storm-dma,
brcm,sr-thermal, amazon,al-thermal, brcm,ocotp, mt8173-mdp, Actions
Owl SPS, Marvell AP80x System Controller, Marvell CP110 System
Controller, cznic,moxtet, and apm,xgene-slimpro-mbox to DT schema
format
- Add i.MX95 fsl,irqsteer, MT8365 Mali Bifrost GPU, Anvo ANV32C81W
EEPROM, and Microchip pic64gx PLIC
- Add missing LGE, AMD Seattle, and APM X-Gene SoC platform
compatibles
- Updates to brcm,bcm2836-l1-intc, brcm,bcm2835-hvs, and bcm2711-hdmi
bindings to fix warnings on BCM2712 platforms
- Drop obsolete db8500-thermal.txt
- Treewide clean-up of extra blank lines and inconsistent quoting
- Ensure all .dtbo targets are applied to a base .dtb
- Speed up dt_binding_check by skipping running validation on empty
examples
DT core:
- Add of_machine_device_match() and of_machine_get_match_data()
helpers and convert users treewide
- Fix bounds checking of address properties in FDT code. Rework the
code to have a single implementation of the bounds checks.
- Rework of_irq_init() to ignore any implicit interrupt-parent (i.e.
in a parent node) on nodes without an interrupt. This matches the
spec description and fixes some RISC-V platforms.
- Avoid a spurious message on overlay removal
- Skip DT kunit tests on RISCV+ACPI"
* tag 'devicetree-for-6.19' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (55 commits)
dt-bindings: kbuild: Skip validating empty examples
dt-bindings: interrupt-controller: brcm,bcm2836-l1-intc: Drop interrupt-controller requirement
dt-bindings: display: Fix brcm,bcm2835-hvs bindings for BCM2712
dt-bindings: display: bcm2711-hdmi: Add interrupt details for BCM2712
of: Skip devicetree kunit tests when RISCV+ACPI doesn't populate root node
soc: tegra: Simplify with of_machine_device_match()
soc: qcom: ubwc: Simplify with of_machine_get_match_data()
powercap: dtpm: Simplify with of_machine_get_match_data()
platform: surface: Simplify with of_machine_get_match_data()
irqchip/atmel-aic: Simplify with of_machine_get_match_data()
firmware: qcom: scm: Simplify with of_machine_device_match()
cpuidle: big_little: Simplify with of_machine_device_match()
cpufreq: sun50i: Simplify with of_machine_device_match()
cpufreq: mediatek: Simplify with of_machine_get_match_data()
cpufreq: dt-platdev: Simplify with of_machine_get_match_data()
of: Add wrappers to match root node with OF device ID tables
dt-bindings: eeprom: at25: Add Anvo ANV32C81W
of/reserved_mem: Simplify the logic of __reserved_mem_alloc_size()
of/reserved_mem: Simplify the logic of fdt_scan_reserved_mem_reg_nodes()
of/reserved_mem: Simplify the logic of __reserved_mem_reserve_reg()
...
91 lines
2.9 KiB
YAML
91 lines
2.9 KiB
YAML
# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/interrupt-controller/aspeed,ast2700-intc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Aspeed AST2700 Interrupt Controller
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description:
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This interrupt controller hardware is second level interrupt controller that
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is hooked to a parent interrupt controller. It's useful to combine multiple
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interrupt sources into 1 interrupt to parent interrupt controller.
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maintainers:
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- Kevin Chen <kevin_chen@aspeedtech.com>
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properties:
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compatible:
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enum:
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- aspeed,ast2700-intc-ic
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reg:
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maxItems: 1
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interrupt-controller: true
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'#interrupt-cells':
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const: 1
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description:
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The first cell is the IRQ number, the second cell is the trigger
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type as defined in interrupt.txt in this directory.
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interrupts:
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minItems: 1
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maxItems: 10
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description: |
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Depend to which INTC0 or INTC1 used.
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INTC0 and INTC1 are two kinds of interrupt controller with enable and raw
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status registers for use.
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INTC0 is used to assert GIC if interrupt in INTC1 asserted.
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INTC1 is used to assert INTC0 if interrupt of modules asserted.
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+-----+ +-------+ +---------+---module0
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| GIC |---| INTC0 |--+--| INTC1_0 |---module2
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| | | | | | |---...
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+-----+ +-------+ | +---------+---module31
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| +---------+---module0
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+---| INTC1_1 |---module2
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| | |---...
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| +---------+---module31
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...
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| +---------+---module0
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+---| INTC1_5 |---module2
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| |---...
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+---------+---module31
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required:
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- compatible
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- reg
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- interrupt-controller
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- '#interrupt-cells'
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- interrupts
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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bus {
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#address-cells = <2>;
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#size-cells = <2>;
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interrupt-controller@12101b00 {
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compatible = "aspeed,ast2700-intc-ic";
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reg = <0 0x12101b00 0 0x10>;
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#interrupt-cells = <1>;
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interrupt-controller;
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interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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