Evan Quan 17252701ec drm/amdgpu: correct the wrong cached state for GMC on PICASSO ... Pair the operations did in GMC ->hw_init and ->hw_fini. That can help to maintain correct cached state for GMC and avoid unintention gate operation dropping due to wrong cached state. BugLink: https://gitlab.freedesktop.org/drm/amd/-/issues/1828 Signed-off-by: Evan Quan <evan.quan@amd.com> Acked-by: Guchun Chen <guchun.chen@amd.com> Reviewed-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2021-12-14 16:09:31 -05:00
..
hwmgr	amdgpu/pm: Modify implmentations of get_power_profile_mode to use amdgpu_pp_profile_name	2021-12-01 16:03:49 -05:00
smumgr	drm/amd/pm: invalidate hdp before CPU access the memory written by GPU	2020-12-08 23:01:24 -05:00
amd_powerplay.c	drm/amdgpu: correct the wrong cached state for GMC on PICASSO	2021-12-14 16:09:31 -05:00
cik_dpm.h
kv_dpm.c	amdgpu/pm: read_sensor() report failure apporpriately	2021-02-26 17:23:49 -05:00
kv_dpm.h
kv_smc.c
Makefile
ppsmc.h
r600_dpm.h
si_dpm.c	drm/amd/pm: Update intermediate power state for SI	2021-09-23 16:35:19 -04:00
si_dpm.h
si_smc.c
sislands_smc.h	drm/amd/pm: Fix out-of-bounds bug	2021-05-10 18:14:49 -04:00