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e75a6b00ad
The Axiado SPI controller is present in AX3000 SoC and Evaluation Board. This controller is operating in Host only mode. Co-developed-by: Prasad Bolisetty <pbolisetty@axiado.com> Signed-off-by: Prasad Bolisetty <pbolisetty@axiado.com> Signed-off-by: Vladimir Moravcevic <vmoravcevic@axiado.com> Link: https://patch.msgid.link/20260107-axiado-ax3000-soc-spi-db-controller-driver-v3-2-726e70cf19ad@axiado.com Signed-off-by: Mark Brown <broonie@kernel.org>
134 lines
4.5 KiB
C
134 lines
4.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Axiado SPI controller driver (Host mode only)
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*
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* Copyright (C) 2022-2025 Axiado Corporation (or its affiliates).
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*/
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#ifndef SPI_AXIADO_H
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#define SPI_AXIADO_H
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/* Name of this driver */
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#define AX_SPI_NAME "axiado-db-spi"
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/* Axiado - SPI Digital Blocks IP design registers */
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#define AX_SPI_TX_FAETR 0x18 // TX-FAETR
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#define ALMOST_EMPTY_TRESHOLD 0x00 // Programmed threshold value
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#define AX_SPI_RX_FAFTR 0x28 // RX-FAETR
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#define ALMOST_FULL_TRESHOLD 0x0c // Programmed threshold value
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#define FIFO_DEPTH 256 // 256 bytes
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#define AX_SPI_CR1 0x00 // CR1
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#define AX_SPI_CR1_CLR 0x00 // CR1 - Clear
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#define AX_SPI_CR1_SCR 0x01 // CR1 - controller reset
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#define AX_SPI_CR1_SCE 0x02 // CR1 - Controller Enable/Disable
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#define AX_SPI_CR1_CPHA 0x08 // CR1 - CPH
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#define AX_SPI_CR1_CPOL 0x10 // CR1 - CPO
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#define AX_SPI_CR2 0x04 // CR2
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#define AX_SPI_CR2_SWD 0x04 // CR2 - Write Enabel/Disable
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#define AX_SPI_CR2_SRD 0x08 // CR2 - Read Enable/Disable
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#define AX_SPI_CR2_SRI 0x10 // CR2 - Read First Byte Ignore
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#define AX_SPI_CR2_HTE 0x40 // CR2 - Host Transmit Enable
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#define AX_SPI_CR3 0x08 // CR3
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#define AX_SPI_CR3_SDL 0x00 // CR3 - Data lines
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#define AX_SPI_CR3_QUAD 0x02 // CR3 - Data lines
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/* As per Digital Blocks datasheet clock frequency range
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* Min - 244KHz
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* Max - 62.5MHz
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* SCK Clock Divider Register Values
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*/
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#define AX_SPI_RX_FBCAR 0x24 // RX_FBCAR
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#define AX_SPI_TX_FBCAR 0x14 // TX_FBCAR
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#define AX_SPI_SCDR 0x2c // SCDR
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#define AX_SPI_SCD_MIN 0x1fe // Valid SCD (SCK Clock Divider Register)
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#define AX_SPI_SCD_DEFAULT 0x06 // Default SCD (SCK Clock Divider Register)
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#define AX_SPI_SCD_MAX 0x00 // Valid SCD (SCK Clock Divider Register)
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#define AX_SPI_SCDR_SCS 0x0200 // SCDR - AMBA Bus Clock source
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#define AX_SPI_IMR 0x34 // IMR
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#define AX_SPI_IMR_CLR 0x00 // IMR - Clear
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#define AX_SPI_IMR_TFOM 0x02 // IMR - TFO
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#define AX_SPI_IMR_MTCM 0x40 // IMR - MTC
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#define AX_SPI_IMR_TFEM 0x10 // IMR - TFE
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#define AX_SPI_IMR_RFFM 0x20 // IMR - RFFM
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#define AX_SPI_ISR 0x30 // ISR
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#define AX_SPI_ISR_CLR 0xff // ISR - Clear
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#define AX_SPI_ISR_MTC 0x40 // ISR - MTC
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#define AX_SPI_ISR_TFE 0x10 // ISR - TFE
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#define AX_SPI_ISR_RFF 0x20 // ISR - RFF
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#define AX_SPI_IVR 0x38 // IVR
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#define AX_SPI_IVR_TFOV 0x02 // IVR - TFOV
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#define AX_SPI_IVR_MTCV 0x40 // IVR - MTCV
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#define AX_SPI_IVR_TFEV 0x10 // IVR - TFEV
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#define AX_SPI_IVR_RFFV 0x20 // IVR - RFFV
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#define AX_SPI_TXFIFO 0x0c // TX_FIFO
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#define AX_SPI_TX_RX_FBCR 0x10 // TX_RX_FBCR
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#define AX_SPI_RXFIFO 0x1c // RX_FIFO
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#define AX_SPI_TS0 0x00 // Target select 0
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#define AX_SPI_TS1 0x01 // Target select 1
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#define AX_SPI_TS2 0x10 // Target select 2
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#define AX_SPI_TS3 0x11 // Target select 3
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#define SPI_AUTOSUSPEND_TIMEOUT 3000
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/* Default number of chip select lines also used as maximum number of chip select lines */
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#define AX_SPI_DEFAULT_NUM_CS 4
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/* Default number of command buffer size */
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#define AX_SPI_COMMAND_BUFFER_SIZE 16 //Command + address bytes
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/* Target select mask
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* 00 – TS0
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* 01 – TS1
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* 10 – TS2
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* 11 – TS3
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*/
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#define AX_SPI_DEFAULT_TS_MASK 0x03
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#define AX_SPI_RX_FIFO_DRAIN_LIMIT 24
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#define AX_SPI_TRX_FIFO_TIMEOUT 1000
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/**
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* struct ax_spi - This definition defines spi driver instance
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* @regs: Virtual address of the SPI controller registers
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* @ref_clk: Pointer to the peripheral clock
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* @pclk: Pointer to the APB clock
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* @speed_hz: Current SPI bus clock speed in Hz
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* @txbuf: Pointer to the TX buffer
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* @rxbuf: Pointer to the RX buffer
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* @tx_bytes: Number of bytes left to transfer
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* @rx_bytes: Number of bytes requested
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* @tx_fifo_depth: Depth of the TX FIFO
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* @current_rx_fifo_word: Buffers the 32-bit word read from RXFIFO
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* @bytes_left_in_current_rx_word: Bytes to be extracted from current 32-bit word
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* @current_rx_fifo_word_for_irq: Buffers the 32-bit word read from RXFIFO for IRQ
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* @bytes_left_in_current_rx_word_for_irq: IRQ bytes to be extracted from current 32-bit word
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* @rx_discard: Number of bytes to discard
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* @rx_copy_remaining: Number of bytes to copy
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*/
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struct ax_spi {
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void __iomem *regs;
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struct clk *ref_clk;
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struct clk *pclk;
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unsigned int clk_rate;
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u32 speed_hz;
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const u8 *tx_buf;
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u8 *rx_buf;
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int tx_bytes;
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int rx_bytes;
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unsigned int tx_fifo_depth;
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u32 current_rx_fifo_word;
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int bytes_left_in_current_rx_word;
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u32 current_rx_fifo_word_for_irq;
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int bytes_left_in_current_rx_word_for_irq;
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int rx_discard;
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int rx_copy_remaining;
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};
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#endif /* SPI_AXIADO_H */
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