mirror of
git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
synced 2026-03-22 07:27:12 +08:00
bf4afc53b7
This was done entirely with mindless brute force, using
git grep -l '\<k[vmz]*alloc_objs*(.*, GFP_KERNEL)' |
xargs sed -i 's/\(alloc_objs*(.*\), GFP_KERNEL)/\1)/'
to convert the new alloc_obj() users that had a simple GFP_KERNEL
argument to just drop that argument.
Note that due to the extreme simplicity of the scripting, any slightly
more complex cases spread over multiple lines would not be triggered:
they definitely exist, but this covers the vast bulk of the cases, and
the resulting diff is also then easier to check automatically.
For the same reason the 'flex' versions will be done as a separate
conversion.
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
123 lines
2.8 KiB
C
123 lines
2.8 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Driver for IDT/Renesas 79RC3243x Interrupt Controller.
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*/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/irqchip.h>
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#include <linux/irqchip/chained_irq.h>
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#include <linux/irqdomain.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#define IDT_PIC_NR_IRQS 32
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#define IDT_PIC_IRQ_PEND 0x00
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#define IDT_PIC_IRQ_MASK 0x08
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struct idt_pic_data {
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void __iomem *base;
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struct irq_domain *irq_domain;
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struct irq_chip_generic *gc;
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};
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static void idt_irq_dispatch(struct irq_desc *desc)
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{
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struct idt_pic_data *idtpic = irq_desc_get_handler_data(desc);
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struct irq_chip *host_chip = irq_desc_get_chip(desc);
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u32 pending, hwirq;
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chained_irq_enter(host_chip, desc);
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pending = irq_reg_readl(idtpic->gc, IDT_PIC_IRQ_PEND);
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pending &= ~idtpic->gc->mask_cache;
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while (pending) {
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hwirq = __fls(pending);
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generic_handle_domain_irq(idtpic->irq_domain, hwirq);
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pending &= ~(1 << hwirq);
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}
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chained_irq_exit(host_chip, desc);
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}
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static int idt_pic_init(struct device_node *of_node, struct device_node *parent)
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{
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struct irq_domain *domain;
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struct idt_pic_data *idtpic;
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struct irq_chip_generic *gc;
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struct irq_chip_type *ct;
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unsigned int parent_irq;
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int ret = 0;
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idtpic = kzalloc_obj(*idtpic);
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if (!idtpic) {
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ret = -ENOMEM;
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goto out_err;
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}
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parent_irq = irq_of_parse_and_map(of_node, 0);
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if (!parent_irq) {
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pr_err("Failed to map parent IRQ!\n");
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ret = -EINVAL;
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goto out_free;
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}
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idtpic->base = of_iomap(of_node, 0);
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if (!idtpic->base) {
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pr_err("Failed to map base address!\n");
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ret = -ENOMEM;
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goto out_unmap_irq;
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}
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domain = irq_domain_create_linear(of_fwnode_handle(of_node), IDT_PIC_NR_IRQS,
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&irq_generic_chip_ops, NULL);
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if (!domain) {
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pr_err("Failed to add irqdomain!\n");
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ret = -ENOMEM;
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goto out_iounmap;
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}
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idtpic->irq_domain = domain;
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ret = irq_alloc_domain_generic_chips(domain, 32, 1, "IDTPIC",
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handle_level_irq, 0,
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IRQ_NOPROBE | IRQ_LEVEL, 0);
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if (ret)
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goto out_domain_remove;
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gc = irq_get_domain_generic_chip(domain, 0);
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gc->reg_base = idtpic->base;
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gc->private = idtpic;
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ct = gc->chip_types;
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ct->regs.mask = IDT_PIC_IRQ_MASK;
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ct->chip.irq_mask = irq_gc_mask_set_bit;
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ct->chip.irq_unmask = irq_gc_mask_clr_bit;
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idtpic->gc = gc;
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/* Mask interrupts. */
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writel(0xffffffff, idtpic->base + IDT_PIC_IRQ_MASK);
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gc->mask_cache = 0xffffffff;
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irq_set_chained_handler_and_data(parent_irq,
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idt_irq_dispatch, idtpic);
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return 0;
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out_domain_remove:
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irq_domain_remove(domain);
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out_iounmap:
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iounmap(idtpic->base);
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out_unmap_irq:
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irq_dispose_mapping(parent_irq);
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out_free:
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kfree(idtpic);
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out_err:
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pr_err("Failed to initialize! (errno = %d)\n", ret);
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return ret;
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}
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IRQCHIP_DECLARE(idt_pic, "idt,32434-pic", idt_pic_init);
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