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012e012e49
'struct qcom_cc_desc' is passed to qcom_cc_map() and qcom_cc_really_probe() only as pointer to const, so make the memory const for safety. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Reviewed-by: Taniya Das <taniya.das@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260128154306.133047-2-krzysztof.kozlowski@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
455 lines
13 KiB
C
455 lines
13 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
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*/
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#include <linux/clk-provider.h>
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#include <linux/mod_devicetable.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <dt-bindings/clock/qcom,sm8750-cambistmclkcc.h>
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#include "clk-alpha-pll.h"
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#include "clk-branch.h"
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#include "clk-rcg.h"
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#include "clk-regmap.h"
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#include "common.h"
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#include "reset.h"
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enum {
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DT_IFACE,
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DT_BI_TCXO,
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DT_BI_TCXO_AO,
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DT_SLEEP_CLK,
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};
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enum {
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P_BI_TCXO,
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P_CAM_BIST_MCLK_CC_PLL0_OUT_EVEN,
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P_CAM_BIST_MCLK_CC_PLL0_OUT_MAIN,
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P_SLEEP_CLK,
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};
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static const struct pll_vco rivian_elu_vco[] = {
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{ 833000000, 1125000000, 0 },
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{ 777000000, 1062000000, 1 },
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};
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/* 960.0 MHz Configuration */
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static const struct alpha_pll_config cam_bist_mclk_cc_pll0_config = {
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.l = 0x32,
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.alpha = 0x0,
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.config_ctl_val = 0x12000000,
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.config_ctl_hi_val = 0x00890263,
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.config_ctl_hi1_val = 0x1af04237,
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.config_ctl_hi2_val = 0x00000000,
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};
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static struct clk_alpha_pll cam_bist_mclk_cc_pll0 = {
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.offset = 0x0,
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.config = &cam_bist_mclk_cc_pll0_config,
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.vco_table = rivian_elu_vco,
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.num_vco = ARRAY_SIZE(rivian_elu_vco),
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_RIVIAN_ELU],
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.clkr = {
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.hw.init = &(const struct clk_init_data) {
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.name = "cam_bist_mclk_cc_pll0",
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.parent_data = &(const struct clk_parent_data) {
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.index = DT_BI_TCXO,
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},
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.num_parents = 1,
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.ops = &clk_alpha_pll_rivian_elu_ops,
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},
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},
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};
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static const struct parent_map cam_bist_mclk_cc_parent_map_0[] = {
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{ P_BI_TCXO, 0 },
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{ P_CAM_BIST_MCLK_CC_PLL0_OUT_EVEN, 3 },
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{ P_CAM_BIST_MCLK_CC_PLL0_OUT_MAIN, 5 },
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};
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static const struct clk_parent_data cam_bist_mclk_cc_parent_data_0[] = {
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{ .index = DT_BI_TCXO },
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{ .hw = &cam_bist_mclk_cc_pll0.clkr.hw },
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{ .hw = &cam_bist_mclk_cc_pll0.clkr.hw },
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};
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static const struct parent_map cam_bist_mclk_cc_parent_map_1[] = {
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{ P_SLEEP_CLK, 0 },
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};
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static const struct clk_parent_data cam_bist_mclk_cc_parent_data_1[] = {
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{ .index = DT_SLEEP_CLK },
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};
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static const struct freq_tbl ftbl_cam_bist_mclk_cc_mclk0_clk_src[] = {
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F(12000000, P_CAM_BIST_MCLK_CC_PLL0_OUT_EVEN, 10, 1, 8),
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F(19200000, P_BI_TCXO, 1, 0, 0),
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F(24000000, P_CAM_BIST_MCLK_CC_PLL0_OUT_EVEN, 10, 1, 4),
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F(68571429, P_CAM_BIST_MCLK_CC_PLL0_OUT_MAIN, 14, 0, 0),
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{ }
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};
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static struct clk_rcg2 cam_bist_mclk_cc_mclk0_clk_src = {
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.cmd_rcgr = 0x4000,
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.mnd_width = 8,
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.hid_width = 5,
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.parent_map = cam_bist_mclk_cc_parent_map_0,
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.freq_tbl = ftbl_cam_bist_mclk_cc_mclk0_clk_src,
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.clkr.hw.init = &(const struct clk_init_data) {
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.name = "cam_bist_mclk_cc_mclk0_clk_src",
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.parent_data = cam_bist_mclk_cc_parent_data_0,
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.num_parents = ARRAY_SIZE(cam_bist_mclk_cc_parent_data_0),
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_rcg2_shared_ops,
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},
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};
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static struct clk_rcg2 cam_bist_mclk_cc_mclk1_clk_src = {
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.cmd_rcgr = 0x401c,
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.mnd_width = 8,
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.hid_width = 5,
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.parent_map = cam_bist_mclk_cc_parent_map_0,
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.freq_tbl = ftbl_cam_bist_mclk_cc_mclk0_clk_src,
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.clkr.hw.init = &(const struct clk_init_data) {
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.name = "cam_bist_mclk_cc_mclk1_clk_src",
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.parent_data = cam_bist_mclk_cc_parent_data_0,
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.num_parents = ARRAY_SIZE(cam_bist_mclk_cc_parent_data_0),
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_rcg2_shared_ops,
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},
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};
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static struct clk_rcg2 cam_bist_mclk_cc_mclk2_clk_src = {
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.cmd_rcgr = 0x4038,
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.mnd_width = 8,
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.hid_width = 5,
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.parent_map = cam_bist_mclk_cc_parent_map_0,
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.freq_tbl = ftbl_cam_bist_mclk_cc_mclk0_clk_src,
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.clkr.hw.init = &(const struct clk_init_data) {
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.name = "cam_bist_mclk_cc_mclk2_clk_src",
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.parent_data = cam_bist_mclk_cc_parent_data_0,
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.num_parents = ARRAY_SIZE(cam_bist_mclk_cc_parent_data_0),
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_rcg2_shared_ops,
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},
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};
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static struct clk_rcg2 cam_bist_mclk_cc_mclk3_clk_src = {
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.cmd_rcgr = 0x4054,
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.mnd_width = 8,
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.hid_width = 5,
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.parent_map = cam_bist_mclk_cc_parent_map_0,
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.freq_tbl = ftbl_cam_bist_mclk_cc_mclk0_clk_src,
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.clkr.hw.init = &(const struct clk_init_data) {
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.name = "cam_bist_mclk_cc_mclk3_clk_src",
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.parent_data = cam_bist_mclk_cc_parent_data_0,
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.num_parents = ARRAY_SIZE(cam_bist_mclk_cc_parent_data_0),
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_rcg2_shared_ops,
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},
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};
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static struct clk_rcg2 cam_bist_mclk_cc_mclk4_clk_src = {
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.cmd_rcgr = 0x4070,
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.mnd_width = 8,
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.hid_width = 5,
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.parent_map = cam_bist_mclk_cc_parent_map_0,
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.freq_tbl = ftbl_cam_bist_mclk_cc_mclk0_clk_src,
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.clkr.hw.init = &(const struct clk_init_data) {
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.name = "cam_bist_mclk_cc_mclk4_clk_src",
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.parent_data = cam_bist_mclk_cc_parent_data_0,
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.num_parents = ARRAY_SIZE(cam_bist_mclk_cc_parent_data_0),
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_rcg2_shared_ops,
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},
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};
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static struct clk_rcg2 cam_bist_mclk_cc_mclk5_clk_src = {
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.cmd_rcgr = 0x408c,
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.mnd_width = 8,
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.hid_width = 5,
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.parent_map = cam_bist_mclk_cc_parent_map_0,
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.freq_tbl = ftbl_cam_bist_mclk_cc_mclk0_clk_src,
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.clkr.hw.init = &(const struct clk_init_data) {
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.name = "cam_bist_mclk_cc_mclk5_clk_src",
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.parent_data = cam_bist_mclk_cc_parent_data_0,
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.num_parents = ARRAY_SIZE(cam_bist_mclk_cc_parent_data_0),
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_rcg2_shared_ops,
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},
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};
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static struct clk_rcg2 cam_bist_mclk_cc_mclk6_clk_src = {
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.cmd_rcgr = 0x40a8,
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.mnd_width = 8,
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.hid_width = 5,
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.parent_map = cam_bist_mclk_cc_parent_map_0,
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.freq_tbl = ftbl_cam_bist_mclk_cc_mclk0_clk_src,
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.clkr.hw.init = &(const struct clk_init_data) {
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.name = "cam_bist_mclk_cc_mclk6_clk_src",
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.parent_data = cam_bist_mclk_cc_parent_data_0,
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.num_parents = ARRAY_SIZE(cam_bist_mclk_cc_parent_data_0),
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_rcg2_shared_ops,
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},
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};
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static struct clk_rcg2 cam_bist_mclk_cc_mclk7_clk_src = {
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.cmd_rcgr = 0x40c4,
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.mnd_width = 8,
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.hid_width = 5,
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.parent_map = cam_bist_mclk_cc_parent_map_0,
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.freq_tbl = ftbl_cam_bist_mclk_cc_mclk0_clk_src,
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.clkr.hw.init = &(const struct clk_init_data) {
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.name = "cam_bist_mclk_cc_mclk7_clk_src",
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.parent_data = cam_bist_mclk_cc_parent_data_0,
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.num_parents = ARRAY_SIZE(cam_bist_mclk_cc_parent_data_0),
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_rcg2_shared_ops,
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},
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};
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static const struct freq_tbl ftbl_cam_bist_mclk_cc_sleep_clk_src[] = {
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F(32000, P_SLEEP_CLK, 1, 0, 0),
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{ }
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};
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static struct clk_rcg2 cam_bist_mclk_cc_sleep_clk_src = {
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.cmd_rcgr = 0x40e0,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = cam_bist_mclk_cc_parent_map_1,
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.freq_tbl = ftbl_cam_bist_mclk_cc_sleep_clk_src,
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.clkr.hw.init = &(const struct clk_init_data) {
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.name = "cam_bist_mclk_cc_sleep_clk_src",
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.parent_data = cam_bist_mclk_cc_parent_data_1,
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.num_parents = ARRAY_SIZE(cam_bist_mclk_cc_parent_data_1),
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_rcg2_shared_ops,
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},
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};
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static struct clk_branch cam_bist_mclk_cc_mclk0_clk = {
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.halt_reg = 0x4018,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x4018,
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data) {
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.name = "cam_bist_mclk_cc_mclk0_clk",
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.parent_hws = (const struct clk_hw*[]) {
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&cam_bist_mclk_cc_mclk0_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch cam_bist_mclk_cc_mclk1_clk = {
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.halt_reg = 0x4034,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x4034,
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data) {
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.name = "cam_bist_mclk_cc_mclk1_clk",
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.parent_hws = (const struct clk_hw*[]) {
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&cam_bist_mclk_cc_mclk1_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch cam_bist_mclk_cc_mclk2_clk = {
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.halt_reg = 0x4050,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x4050,
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data) {
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.name = "cam_bist_mclk_cc_mclk2_clk",
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.parent_hws = (const struct clk_hw*[]) {
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&cam_bist_mclk_cc_mclk2_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch cam_bist_mclk_cc_mclk3_clk = {
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.halt_reg = 0x406c,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x406c,
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data) {
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.name = "cam_bist_mclk_cc_mclk3_clk",
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.parent_hws = (const struct clk_hw*[]) {
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&cam_bist_mclk_cc_mclk3_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch cam_bist_mclk_cc_mclk4_clk = {
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.halt_reg = 0x4088,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x4088,
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data) {
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.name = "cam_bist_mclk_cc_mclk4_clk",
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.parent_hws = (const struct clk_hw*[]) {
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&cam_bist_mclk_cc_mclk4_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch cam_bist_mclk_cc_mclk5_clk = {
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.halt_reg = 0x40a4,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x40a4,
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data) {
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.name = "cam_bist_mclk_cc_mclk5_clk",
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.parent_hws = (const struct clk_hw*[]) {
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&cam_bist_mclk_cc_mclk5_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch cam_bist_mclk_cc_mclk6_clk = {
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.halt_reg = 0x40c0,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x40c0,
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data) {
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.name = "cam_bist_mclk_cc_mclk6_clk",
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.parent_hws = (const struct clk_hw*[]) {
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&cam_bist_mclk_cc_mclk6_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch cam_bist_mclk_cc_mclk7_clk = {
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.halt_reg = 0x40dc,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x40dc,
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data) {
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.name = "cam_bist_mclk_cc_mclk7_clk",
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.parent_hws = (const struct clk_hw*[]) {
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&cam_bist_mclk_cc_mclk7_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_regmap *cam_bist_mclk_cc_sm8750_clocks[] = {
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[CAM_BIST_MCLK_CC_MCLK0_CLK] = &cam_bist_mclk_cc_mclk0_clk.clkr,
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[CAM_BIST_MCLK_CC_MCLK0_CLK_SRC] = &cam_bist_mclk_cc_mclk0_clk_src.clkr,
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[CAM_BIST_MCLK_CC_MCLK1_CLK] = &cam_bist_mclk_cc_mclk1_clk.clkr,
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[CAM_BIST_MCLK_CC_MCLK1_CLK_SRC] = &cam_bist_mclk_cc_mclk1_clk_src.clkr,
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[CAM_BIST_MCLK_CC_MCLK2_CLK] = &cam_bist_mclk_cc_mclk2_clk.clkr,
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[CAM_BIST_MCLK_CC_MCLK2_CLK_SRC] = &cam_bist_mclk_cc_mclk2_clk_src.clkr,
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[CAM_BIST_MCLK_CC_MCLK3_CLK] = &cam_bist_mclk_cc_mclk3_clk.clkr,
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[CAM_BIST_MCLK_CC_MCLK3_CLK_SRC] = &cam_bist_mclk_cc_mclk3_clk_src.clkr,
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[CAM_BIST_MCLK_CC_MCLK4_CLK] = &cam_bist_mclk_cc_mclk4_clk.clkr,
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[CAM_BIST_MCLK_CC_MCLK4_CLK_SRC] = &cam_bist_mclk_cc_mclk4_clk_src.clkr,
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[CAM_BIST_MCLK_CC_MCLK5_CLK] = &cam_bist_mclk_cc_mclk5_clk.clkr,
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[CAM_BIST_MCLK_CC_MCLK5_CLK_SRC] = &cam_bist_mclk_cc_mclk5_clk_src.clkr,
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[CAM_BIST_MCLK_CC_MCLK6_CLK] = &cam_bist_mclk_cc_mclk6_clk.clkr,
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[CAM_BIST_MCLK_CC_MCLK6_CLK_SRC] = &cam_bist_mclk_cc_mclk6_clk_src.clkr,
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[CAM_BIST_MCLK_CC_MCLK7_CLK] = &cam_bist_mclk_cc_mclk7_clk.clkr,
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[CAM_BIST_MCLK_CC_MCLK7_CLK_SRC] = &cam_bist_mclk_cc_mclk7_clk_src.clkr,
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[CAM_BIST_MCLK_CC_PLL0] = &cam_bist_mclk_cc_pll0.clkr,
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[CAM_BIST_MCLK_CC_SLEEP_CLK_SRC] = &cam_bist_mclk_cc_sleep_clk_src.clkr,
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};
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|
|
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static struct clk_alpha_pll *cam_bist_mclk_cc_sm8750_plls[] = {
|
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&cam_bist_mclk_cc_pll0,
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|
};
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|
|
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static u32 cam_bist_mclk_cc_sm8750_critical_cbcrs[] = {
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0x40f8, /* CAM_BIST_MCLK_CC_SLEEP_CLK */
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|
};
|
|
|
|
static const struct regmap_config cam_bist_mclk_cc_sm8750_regmap_config = {
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|
.reg_bits = 32,
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|
.reg_stride = 4,
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|
.val_bits = 32,
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.max_register = 0x5010,
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|
.fast_io = true,
|
|
};
|
|
|
|
static struct qcom_cc_driver_data cam_bist_mclk_cc_sm8750_driver_data = {
|
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.alpha_plls = cam_bist_mclk_cc_sm8750_plls,
|
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.num_alpha_plls = ARRAY_SIZE(cam_bist_mclk_cc_sm8750_plls),
|
|
.clk_cbcrs = cam_bist_mclk_cc_sm8750_critical_cbcrs,
|
|
.num_clk_cbcrs = ARRAY_SIZE(cam_bist_mclk_cc_sm8750_critical_cbcrs),
|
|
};
|
|
|
|
static const struct qcom_cc_desc cam_bist_mclk_cc_sm8750_desc = {
|
|
.config = &cam_bist_mclk_cc_sm8750_regmap_config,
|
|
.clks = cam_bist_mclk_cc_sm8750_clocks,
|
|
.num_clks = ARRAY_SIZE(cam_bist_mclk_cc_sm8750_clocks),
|
|
.use_rpm = true,
|
|
.driver_data = &cam_bist_mclk_cc_sm8750_driver_data,
|
|
};
|
|
|
|
static const struct of_device_id cam_bist_mclk_cc_sm8750_match_table[] = {
|
|
{ .compatible = "qcom,sm8750-cambistmclkcc" },
|
|
{ }
|
|
};
|
|
MODULE_DEVICE_TABLE(of, cam_bist_mclk_cc_sm8750_match_table);
|
|
|
|
static int cam_bist_mclk_cc_sm8750_probe(struct platform_device *pdev)
|
|
{
|
|
return qcom_cc_probe(pdev, &cam_bist_mclk_cc_sm8750_desc);
|
|
}
|
|
|
|
static struct platform_driver cam_bist_mclk_cc_sm8750_driver = {
|
|
.probe = cam_bist_mclk_cc_sm8750_probe,
|
|
.driver = {
|
|
.name = "cambistmclkcc-sm8750",
|
|
.of_match_table = cam_bist_mclk_cc_sm8750_match_table,
|
|
},
|
|
};
|
|
|
|
module_platform_driver(cam_bist_mclk_cc_sm8750_driver);
|
|
|
|
MODULE_DESCRIPTION("QTI CAMBISTMCLKCC SM8750 Driver");
|
|
MODULE_LICENSE("GPL");
|