4 Commits

Author	SHA1	Message	Date
Geert Uytterhoeven	a05de66ea6	Merge branch 'rcar-rst' into clk-renesas-for-v4.10 ... soc: renesas: Add R-Car RST driver for obtaining mode pin state	2016-11-02 20:53:26 +01:00
Geert Uytterhoeven	ddab5aed8e	clk: renesas: rcar-gen3-cpg: Remove obsolete rcar_gen3_read_mode_pins() ... All R-Car Gen3 clock drivers now obtain the values of the mode pins from the R-Car RST driver. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Dirk Behme <dirk.behme@de.bosch.com> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>	2016-11-02 20:43:59 +01:00
Geert Uytterhoeven	30ad3cf00e	clk: renesas: rcar-gen3-cpg: Always use readl()/writel() ... The R-Car Gen3 CPG/MSSR driver uses a mix of clk_readl()/clk_writel() and readl()/writel() to access the clock registers. Settle on the generic readl()/writel(). Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Stephen Boyd <sboyd@codeaurora.org>	2016-10-17 15:56:21 +02:00
Geert Uytterhoeven	5b1defde70	clk: renesas: cpg-mssr: Extract common R-Car Gen3 support code ... Extract the code to support parts common to all members of the R-Car Gen3 SoC family into a separate file, to ease sharing among SoC-specific drivers. Note that while the cpg_pll_configs[] arrays and the selection of the config based on the MODE bits are identical on R-Car H3 and R-Car M3-W, they are not common, and may be different on other R-Car Gen3 SoCs. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Tested-by: Simon Horman <horms+renesas@verge.net.au>	2016-06-06 11:58:31 +02:00